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AFE5801- CPOL/ CPHA + SCLK troubleshooting

MOHIT KAPUR
Prodigy 100 points
Other Parts Discussed in Thread: AFE5801

I am attempting to verify the SPI serial link between my test equipment and TI AFE5801. I am unable to see SCLK. Help would be greatly appreciated.

First. are CPOL (Clock Polarity)= 0 & CPHA (Clock Phase)= 1 for TI AFE5801? Refer pg. 25 (read), pg. 20 (write) of AFE5801 datasheet

I can't see the SCLK. Would incorrect value for CPOL & CPHA prevent me from viewing SCLK in the Oscilloscope? My sequence is to set the power  supply, set the RESET low, and then set CS low. I used the delays shown on pg. 19 (Fig 35) of AFE5801 datasheet.

We do not have a TSW1250EVM. AFE5801 is designed in on our Motherboard. I have been able to generate a 40 MHz square wave with FPGA on my Motherboard (different program, to verify hardware and cabling)

Second, assuming the code is written correctly- could you please tell me the critical pins that could disable SCLK when their logic is set incorrectly ? (e.g. will I see SCLK if RESET, SEN pins have logic 1)

Third, can SCLK work at 5 MHz? (pg. 19 of AFE5801 datasheet)

Pointers on how one should go about troubleshooting no SCLK are most welcome.

Thanks,

Mohit Kapur

  • 0
    TI__Mastermind 18275 points

    MOHIT,

    We have received your request regarding the AFE5801 and hope to get back to you with a response shortly.

  • 0
    TI__Expert 6320 points

    Hi Mohit,

    I have seen this post and I will respond in the next few days. Are you saying that the SCLK output of your FPGA has no activity?  SCLK can work up to 20MHz, but 5MHz should be ok.

    Thanks,

    Chuck Smyth

  • 0 in reply to Chuck Smyth
    Prodigy 100 points

    I am glad you saw this post. 5 MHz SCLK takes care of my third question.

    Yes, I do not see SCLK on the Oscilloscope. Would you have suggestions on critical pins to check that could potentially disable SCLK on AFE5801?

    I look forward to your response.

    Thanks,

    Mohit Kapur

  • 0 in reply to MOHIT KAPUR
    Prodigy 100 points

    I will answer my post in case this benefits someone else.

    Incorrect value for CPOL & CPHA does not disable SCLK.

    CPOL (Clock Polarity)= 0 & CPHA (Clock Phase)= 1 works for my program.

    AFE5801 ignores SCLK & SDATA when SEN is high. Hence, we need to check SEN.

    Thanks,  

    Mohit Kapur

  • 0 in reply to MOHIT KAPUR
    Prodigy 100 points

    I was incorrect about CPOL. CPOL =1 for AFE5801. Please refer to either pg. 25 (read), pg. 20 (write) of AFE5801 datasheet. CPOL (Clock Polarity)= 1 since SCLK starts high and falling edge is the first edge of transmission.

    CPHA is either 0 or 1, not sure.  Mode 3 (CPOL=1, CPHA=1) also works in my program.

    Hopefully, someone benefits

    Thanks,

    Mohit Kapur