AFE5808A part ADC output in offset binary and 2's complete format

Chandu,

From the DS, page 30:

Users can write the required VALUE into register
bits <CUSTOM PATTERN> which is Register 5[13:0]. Then the device will output VALUE at its outputs,
about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24
SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing
Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may
not be high. For example, 128 points custom pattern will take approximately 128 × (24 SCLK clock cycles +
4 ADC clock cycles).
NOTE
Only one of the above patterns can be active at any given instant.

The output of the device would be:

0x3FFF,0x3FFF,0x3FFF,0x3FFF,0x3FFF,..... 0x2000, 0x2000,0x2000,0x2000,0x2000,.... 0x3000, 0x3000,0x3000,0x3000,0x3000,...... 0x1900,0x1900,0x1900,0x1900,....

This is independent of 2's complement or Offset binary. The number of repetitions of each value depends on the speed of the SPI, as stated above.  The fastest refresh rate possible would be 24 SCLK cycles + 4 ADC clock cycles

 

Thanks,

 

Chuck Smyth

Hi,
1) According data sheet of AFE5808, by default the ADC is capable of generating 14 bit signed 2's complement. It can also be configured to 12 bit. Am i right?
2) I configured the AFE as 16x serialization data rate (3[14:13]=01), 14 bit ADC resolution (4[1]=0), Using TSW1400 for ADC signal capturing and ultrasound echo signal at input then after saving the capture into csv file, I observed the ADC codes are b/w -32768 to 32767
But here my doubt is the range should be b/w -8192 to 8191 for 16x or 14x serialization rate, because the ADC resolution is 14 bit (ADC values are b/w -8192 to 8191). In 16x mode, two 0's are added.

How the 14bit ADC data is serially sent out in 16x mode?

Hi all, 

Please can somebody clarify my doubt mentioned in previous  post.

Thank you.

Reards,

chandu.

1) According data sheet of AFE5808, by default the ADC is capable of generating 14 bit signed 2's complement. It can also be configured to 12 bit. Am i right?  The device is, but the EVM GUI might set it to offset binary by default.  Yes, it can be 12-bit as well.

2) I configured the AFE as 16x serialization data rate (3[14:13]=01), 14 bit ADC resolution (4[1]=0), Using TSW1400 for ADC signal capturing and ultrasound echo signal at input then after saving the capture into csv file, I observed the ADC codes are b/w -32768 to 32767.

But here my doubt is the range should be b/w -8192 to 8191 for 16x or 14x serialization rate, because the ADC resolution is 14 bit (ADC values are b/w -8192 to 8191). In 16x mode, two 0's are added.  No, in 16x mode, the 0s are added to the LSBs, therefore the scale will shift. The new scale will be 64k wide instead of 16k wide, independent of the ADC resolution.

How the 14bit ADC data is serially sent out in 16x mode? Here 16 bit means 16x