Hi, I am using VSP3210 with Hamamatsu CCD sensor (S8982) . The circuit does not work properly. The circuit assembled on 4 layer PCB with separate DGND and AGND (in one layer) joined at one point under ADC and separated by cutouts,similarly for digital and analog power supply. Analog supply obtained from digital and isolated from digital.
ADCCK 1 Mhz
CK1 rise 300ns after ADCCK rise, fall 100ns before ADCCK fall
CK2 rise 300 ns after ADCCK fall, fall 100ns before ADCCK rise
ADC used in 1-CCD mode; for signal from CCD used Red channel. Config Reg = 0x88; Red Bias = 0x200;Red Gain = 0x00;
/OE = GND allways; CLP = VCC during unused black pixels; VDRV = +3.3V;
Problem is the next: When I don't connect CCD to my board, and Input signal coupled from DC by 0.1 uF. R = 5.1 kOh input resistor for emitter follower for CCD. I see several spikes on my picture (all pixel is a noise near 12 rms). Spikes have constant amplitude max - min codes from ADC (0x4FF(1279) - 0x200 (512)= 0x2FF (767) ) and consist from two pixel with min code and next with max code. If I change gain to 5 from 0 or change only bias to 0x1FD I see much more spikes on my picture.
I think it may be wrong ADC convert. What do you suggest me for correct this problem?
Could you please
send the emitter follower portion of the circuit and a sample of the data.
The register settings being used for teh VSP3210
Also, could you please try grounding input to the AFE with 0.1uF cap and taking measurements. You should see a small signal with a standard deviation of approx 10 LSB.
Problem are solved. It was error in FPGA code which read hi and low bytes from different ADC words.
When ADC output code near 0x01FF,0x0200,0x01FF FPGA captured 0x02FF and 0x0100 codes. That codes I was see as spikes
with very stable amplitude.
Glad to hear the byte order issue was resolved. Swapping bytes or swapping big-endian/little-endian bit order is not unusual in fpga interfaces to the AFE.
One practice is to build in a little test counter in the FPGA that can be mux'ed into the AFE input path in the FPGA.Then increment the counter and read the FPGA data path to verify the bit order and byte order of the data path. The counter can be removed later in the design cycle.
Also, some TI AFEs have the ability to generate a digital test ramp on the outputs as part of a test mode. This is also useful for verifying bit and byte orders. Unfortunately, the VSP3xxxx devices do not have this capability.
I iwll mark this thread as answered unless you have further questions on the topic,
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.