AFE5801- DCLK 60 MHz or 120 MHz?

MOHIT KAPUR

Other Parts Discussed in Thread: AFE5801

Please refer to pg. 9 of AFE5801 datasheet. I am debugging subroutines to:

deserialize the LVDS data on DCLK (bit clock) rising & falling edge {inner While Loop}
capture the complete word on FCLK (frame clock) rising edge {outer While Loop}

Assume FCLK (frame clock) = 10 MHz. Per the figure, DCLK= 6 * 10 or 60 MHz. I am confused on the rate at which the inner or deserialize While Loop should execute. DCLK is DDR, i.e. we strobe the data on DCLK rising and falling edge. Should the inner or deserialize While Loop run at 120 MHz {60 *2 (rising + falling), DDR} or 60 MHz in this case?

Thanks,

Mohit Kapur

over 9 years ago

0 Chuck Smyth over 9 years ago

TI__Expert 6320 points

LVDS Interface Appnote.pdfHi Mohit,

The highest frequency coming from the AFE5801 is 60MHz. This DCLK should be the input to the DDR module. Please see figure 2-1 of the app note.

Thanks,

Chuck Smyth

0 MOHIT KAPUR over 9 years ago in reply to Chuck Smyth

Prodigy 100 points

Hello Chuck:

Thanks for the clarification. Assuming FCLK (frame clock) = 10 MHz, rate at which the inner or deserialize While Loop should execute is
60 MHz.

FYI- We need to build DDR logic block + Serial-Parallel Shift Register ourselves in LabVIEW, not part of NI logic library. The App Note is very helpful, thank you!

I will start another thread for separate topic since I do not find the answer in the forums.

Thanks,

Mohit Kapur

0 Chuck Smyth over 9 years ago in reply to MOHIT KAPUR

TI__Expert 6320 points

Mohit,

I don't understand what you mean. Are you capturing the raw data with the FPGA DDR logic block and then post-processing in Labview?

Thanks,

Chuck

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AFE5801- DCLK 60 MHz or 120 MHz?