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we are designing a prototype for our small xray system using cmos sensor M118-232C3. I want to know can we use LM98725 with this CIS module and how?
I think the LM98725 should be OK for that sensor, link shown below. The only small concern is about the black voltage level of the sensor ("Analog output voltage at dark paper") being around 0.4V where you might be on the low end of the input linear voltage range.
M118-232C3 from CMOS Sensors Inc.
For your application you would be using Mode 3, 3 Color Sequence, CISb operating mode. See Figure 46 in the datasheet timing diagram.
In reply to Hooman Hashemi:
In reply to Martin Wolf11:
Its okay take your time but let me know how to configure my CIS module with LM98725 or if you know anyother better AFE for this. My application is to convert the Xrays analog signal to digital for my FPGA.
First of all I want to thank you for your support and concern. I have listed down some of my questions:
I'm using sensor in Mode 3 but as I have already said that I don't need to turn on the RGB lamps of the sensor because in my application sensor has to detect the x-rays passed by a small body organ and gives electric signal. My sensor has 3 inputs for RGB lamps so should I still connect SH1, SH3 and SH4 to these sensor input or not?
Yes I'm using CMOS data output in this case SH2/CLKOUT should be connected to the FPGA as a DATA clock.
So now I have to connect SH5 pin to the sensor SP pin which controls wen each new line of scan begins and end right? and PHIA1 to the CP.
I*m using master timing generation mode.
Why resistors should be used with the clock?
What is the difference between PIXEL CLOCK and ADC CLOCK and which one should I need and configure if I used a sensor at 5MHz?
VCLP pins sets the reference level voltage which will be detected with the CLAMP pulse?
What is SH interval and its different states I didn't understand it.
How to configure registers via serial interfacing?
I know how busy you are, so I really appreciate in advance the time you have to give me. As this field is new to me so I has a very hard time understanding and remembering the concepts.
We understand your usage needs better now.
Since you are using the CIS in monochrome mode, with the same illumination color (X-ray) for every line, you should be using Mode 3, with a single line sequence. This is shown in Figure 48 of the datasheet. Since you don't need to turn the RGB lamps on then you don't need to enable or connect any of those signals.
As your illumination is coming from outside the sensor, you should tie all of the lamp control pins of the CIS sensor to Ground so the sensor internal drive transistors are off.
If your pixel sample rate is 5 MHz I recommend you use a 5 MHz pixel rate input clock to the LM98725 AFE. It will multiply this up by 3x to create the internal ADC clock.
Once your have the sensor clocking working you can adjust the PIXPHASE, CLAMP and SAMPLE settings to align the AFE sampling event to the CIS pixel output timing. See Figure 24 and Figure 28 of the datasheet. Since this is a CIS sensor, you'll need to use S/H mode so the CLAMP and SAMPLE timings should be set the same. The reference voltage sampled is from the VCLP.
CIS sensors like this one only require a single clock for the SP signal, once per line. CCD sensors can require much more complex Shift pulses (transferring charge from the pixel sensing array to the CCD transfer array). Sometimes the high resolution sensors even need different timing for different lines in their sequence. That is what the multiple SH interval feature is primarily intended for.
For the CIS sensor you have, you just need to make the SP signal go high for 1 pixel period. So you probably will only have one SH interval with 1 or a few states. The SP signal will be programmed to be low during the line portion and high during a single pixel period in the SH interval.
Since you are using CMOS data output mode, there isn’t any bit tag information sent to your FPGA. For that reason I recommend you also connect the PHIA1 signal to your FPGA. Alternatively we can make a duplicate of this signal on another output (SH1, etc.) to send to the FPGA. This will let the FPGA know when the start of line is for data alignment purposes. If you use a different SH output (than used for CP) you could program this signal to go high and low at the beginning and end of valid pixel data.
I have attached a starting point register set for your needs. These settings would be loaded and then a final write to Page 0 Register 0 with value 0x23h must be done to Lock the registers and start AFE operation.
LM98725 E2E 5_15_16.dat
Hope this helps.
I've got the following response from a more experienced colleague with regard to your LM98725 questions. I've shown the responses in color below.
When I provide 5MHz INCLK to LM98725 the output clock from PHIA1 whould also be 5MHz for the sensor or do I need to configure/program it? For 5 MHz input clock and configuration set to INCLK at PIXCLK rate, the PHIA1 frequency can be programmed to be at 2.5, 5 MHz, or higher frequencies. Settings controlling the waveform frequency for PHIA are in Register Page 6, Address 0-5 and Address 1Eh. These must be set as needed, the power-on default values will not provide output clock waveforms.
And how I can programmed my SH interval? The number of pixels between SH Intervals (aka the line length) is set in Register Page 2, Address Dh, Eh and Fh. The waveform behavior during the SH interval is controlled by the settings of Register Pages 3, 4 and 5. To select my INCLK = PIXCLK I have to make this configuration (page 0, register 02, bit 2 = 1) but in the register settings that you sent me its written SPI_SENDDATA(0x02C2); To set INCLK = PIXCLK we need to set bit 2=1. For a 3 output CCD sensor I would recommend setting Page 0, Register 2 to C6h. This will give:
If we sent a file with this register set to C2h that was in error. My apologies. Please also tell me how to do a serial interfacing to send data to ADC chip.
The serial interface must comply with the sequence/timing shown in Figures 62-67. There are a few different possible modes of operation of the interface that should provide the needed flexibility to allow a wide range of control devices (ie. uC, uP, FPGA) to work with the LM98725.
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