Hello experts,
we are designing a prototype for our small xray system using cmos sensor M118-232C3. I want to know can we use LM98725 with this CIS module and how?
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Hi Martin,
I think the LM98725 should be OK for that sensor, link shown below. The only small concern is about the black voltage level of the sensor ("Analog output voltage at dark paper") being around 0.4V where you might be on the low end of the input linear voltage range.
M118-232C3 from CMOS Sensors Inc.
For your application you would be using Mode 3, 3 Color Sequence, CISb operating mode. See Figure 46 in the datasheet timing diagram.
Regards,
Hooman
Hi Hooman,
Its okay take your time but let me know how to configure my CIS module with LM98725 or if you know anyother better AFE for this. My application is to convert the Xrays analog signal to digital for my FPGA.
Thank you.
Kind Regards,
Martin
Hello Hooman,
First of all I want to thank you for your support and concern. I have listed down some of my questions:
I'm using sensor in Mode 3 but as I have already said that I don't need to turn on the RGB lamps of the sensor because in my application sensor has to detect the x-rays passed by a small body organ and gives electric signal. My sensor has 3 inputs for RGB lamps so should I still connect SH1, SH3 and SH4 to these sensor input or not?
Yes I'm using CMOS data output in this case SH2/CLKOUT should be connected to the FPGA as a DATA clock.
So now I have to connect SH5 pin to the sensor SP pin which controls wen each new line of scan begins and end right? and PHIA1 to the CP.
I*m using master timing generation mode.
Why resistors should be used with the clock?
What is the difference between PIXEL CLOCK and ADC CLOCK and which one should I need and configure if I used a sensor at 5MHz?
PIXPHASE?
VCLP pins sets the reference level voltage which will be detected with the CLAMP pulse?
What is SH interval and its different states I didn't understand it.
How to configure registers via serial interfacing?
I know how busy you are, so I really appreciate in advance the time you have to give me. As this field is new to me so I has a very hard time understanding and remembering the concepts.
Kind Regards,
Martin
Hi Martin,
We understand your usage needs better now.
Since you are using the CIS in monochrome mode, with the same illumination color (X-ray) for every line, you should be using Mode 3, with a single line sequence. This is shown in Figure 48 of the datasheet. Since you don't need to turn the RGB lamps on then you don't need to enable or connect any of those signals.
As your illumination is coming from outside the sensor, you should tie all of the lamp control pins of the CIS sensor to Ground so the sensor internal drive transistors are off.
If your pixel sample rate is 5 MHz I recommend you use a 5 MHz pixel rate input clock to the LM98725 AFE. It will multiply this up by 3x to create the internal ADC clock.
Once your have the sensor clocking working you can adjust the PIXPHASE, CLAMP and SAMPLE settings to align the AFE sampling event to the CIS pixel output timing. See Figure 24 and Figure 28 of the datasheet. Since this is a CIS sensor, you'll need to use S/H mode so the CLAMP and SAMPLE timings should be set the same. The reference voltage sampled is from the VCLP.
CIS sensors like this one only require a single clock for the SP signal, once per line. CCD sensors can require much more complex Shift pulses (transferring charge from the pixel sensing array to the CCD transfer array). Sometimes the high resolution sensors even need different timing for different lines in their sequence. That is what the multiple SH interval feature is primarily intended for.
For the CIS sensor you have, you just need to make the SP signal go high for 1 pixel period. So you probably will only have one SH interval with 1 or a few states. The SP signal will be programmed to be low during the line portion and high during a single pixel period in the SH interval.
Since you are using CMOS data output mode, there isn’t any bit tag information sent to your FPGA. For that reason I recommend you also connect the PHIA1 signal to your FPGA. Alternatively we can make a duplicate of this signal on another output (SH1, etc.) to send to the FPGA. This will let the FPGA know when the start of line is for data alignment purposes. If you use a different SH output (than used for CP) you could program this signal to go high and low at the beginning and end of valid pixel data.
I have attached a starting point register set for your needs. These settings would be loaded and then a final write to Page 0 Register 0 with value 0x23h must be done to Lock the registers and start AFE operation.
Hope this helps.
Regards,
Hooman
Hi Martin,
I've got the following response from a more experienced colleague with regard to your LM98725 questions. I've shown the responses in color below.
When I provide 5MHz INCLK to LM98725 the output clock from PHIA1 whould also be 5MHz for the sensor or do I need to configure/program it? For 5 MHz input clock and configuration set to INCLK at PIXCLK rate, the PHIA1 frequency can be programmed to be at 2.5, 5 MHz, or higher frequencies. Settings controlling the waveform frequency for PHIA are in Register Page 6, Address 0-5 and Address 1Eh. These must be set as needed, the power-on default values will not provide output clock waveforms.
And how I can programmed my SH interval? The number of pixels between SH Intervals (aka the line length) is set in Register Page 2, Address Dh, Eh and Fh. The waveform behavior during the SH interval is controlled by the settings of Register Pages 3, 4 and 5.
To select my INCLK = PIXCLK I have to make this configuration (page 0, register 02, bit 2 = 1) but in the register settings that you sent me its written SPI_SENDDATA(0x02C2); To set INCLK = PIXCLK we need to set bit 2=1. For a 3 output CCD sensor I would recommend setting Page 0, Register 2 to C6h. This will give:
If we sent a file with this register set to C2h that was in error. My apologies.
Please also tell me how to do a serial interfacing to send data to ADC chip.
The serial interface must comply with the sequence/timing shown in Figures 62-67. There are a few different possible modes of operation of the interface that should provide the needed flexibility to allow a wide range of control devices (ie. uC, uP, FPGA) to work with the LM98725.
Regards,
Hooman
Hi Hooman,
Thanks for your detail answer.
For my CIS sensor SP signal, I set only one SH state length i.e SH State 0 on Page 3 Register 0 and all other state lengths should be zero because I need signal to go high only once. Furthermore I select SH1 to go high at SH state zero (Page 5 Register 0 Bit 0 = 1) and connect this SH1 to my CIS SP signal pin. This is Okay?
My CIS sensor is getting CP from PHIA1, for this purpose I did following configuration:
INCLK = PIXCLK = 5MHz
Page 6 Register 1E Bit 4 = 0 (for 5MHz PHIA)
But I don’t understand how should I configure registers 0 to 5 on page 6 for PHIA and what are their functions? You told me to configure them as well in your last message.
There is a description about CE pin (chip enable) on page 84 should I connect it to the GND?
Regards,
Martin
Hi Martin,
Some responses to your questions in color below.
For my CIS sensor SP signal, I set only one SH state length i.e SH State 0 on Page 3 Register 0 and all other state lengths should be zero because I need signal to go high only once. Furthermore I select SH1 to go high at SH state zero (Page 5 Register 0 Bit 0 = 1) and connect this SH1 to my CIS SP signal pin. This is Okay? This sounds OK. If possible please share a schematic/sketch so we can verify the connections.
My CIS sensor is getting CP from PHIA1, for this purpose I did following configuration:
INCLK = PIXCLK = 5MHz This is correct.
Page 6 Register 1E Bit 4 = 0 (for 5MHz PHIA) This is correct.
But I don’t understand how should I configure registers 0 to 5 on page 6 for PHIA and what are their functions? You told me to configure them as well in your last message. There are 42 bit-times during one pixel period. The 42 bit pattern in these registers sets the output waveform of the PHIA timing generator for one pixel period. When the bits are 0s the output is low, and when the bits are 1s the output is high. For a simplistic case if the first 21 bits are 0 and the next 21 bits are 1 then the output waveform will be a 50% duty cycle square wave, which is the desired waveform for this sensor input.
There is a description about CE pin (chip enable) on page 84 should I connect it to the GND? The CE pin can be logic low (DGND), logic high (connected to VD) or left open circuit (floating). The state of this pin determines the values of the 2 CE bits in the address field of the serial interface timing diagram. This allows multiple LM98725 devices to share a common SPI bus if needed.
Regards,
Hooman
Hello Hooman,
I haven't design schematic for the project yet right now I'm just configuring the registers through Arduino UNO (easy and fast) via SPI just to check the response of the LM98725 on oscilloscope. My final SPI configuration would be with FPGA (on which I'm still working).
My connections between sensor and lm98725 would be like this:
Sensor =>> LM98725
SP SH1
CP PHIA1
Vout1 OSr
Vout2 OSb
Vout3 OSg
Dout (0-7) => FPGA
I want to know about the voltages of SCLK and the SDI, my Arduino SCLK voltages are 4.7V and on SDI pins it sends data which high logic is upto 5V. Is there any voltages limit for the clock and SDI data like 3.3V or 5V is okay?
As I'm using only one slave so I connect CE pin to the GND and send CE bits (00), its okay or should I left then unconnected and send bits (10) ?
Maximum voltage limit for SH_R Pulse?
How can I access different pages of registers, my Arduino sends 8 bits at once so I have choose to send 16 bits in two steps. First 8 then next 8.
For Example if I want to access page 3 and configure register :
void loop()
{
digitalWrite(SEN, LOW);
SPI.transfer(0x1F); //Page 0 first 8 bits
SPI.transfer(0x00); //Page 0 next 8 bits
digitalWrite(SEN, HIGH);
digitalWrite(SEN, LOW);
SPI.transfer(0x02); //Register 2 first 8 bits
SPI.transfer(0xC4); // Register 2 next 8 bits
digitalWrite(SEN, HIGH);
digitalWrite(SEN, LOW);
SPI.transfer(0x1F); //Page 1 first 8 bits
SPI.transfer(0x01); //Page 1 next 8 bits
digitalWrite(SEN, HIGH);
}
I need to set the SH state length (0) to high for a short period (100ns) like in the picture I have attached. How can I configure registers 0-3 on page 7 for SH1 pixel on off. but there are 8
Hi Martin,
I'm asking other colleagues to help me answer your questions and I've been promised to get their time by this Friday July 1.
Sorry about the delay.
Regards,
Hooman
Hello Martin,
This is a 3.3V part and the abs max voltage as shown in the datasheet is 4.2V, with current limited. Vih is 2V. I would recommend keeping the input voltages less than the supply voltage so you don't need to be as concerned about a current limit to these pins.
We are working on your other questions.
Here is the schematic of my PCB circuit, I have configured the registers but still didn't get any output frequency from the chip can you please where the problem could be?
I need 5MHz output clock from PHIA1 and a SH1 interval with only one SH state.
I'm sending you register configuration that I did, I used Arduino UNO to perform registers configuration via SPI.
I used 16+ clock with 4 wires. CE pin is connedted to the VD (CE bits are 01 then)
At first I send Dummy Bits to get 16 clocks and data values of last configured register and then the actual 16 bits.
Please have a look on register values data below and let me know where the problem is as soon as possible.
#include <SPI.h>
int ss=10; // using digital pin 10 for SPI slave select
int DATAOUT=11; //MOSI
int DATAIN=12; //MISO - not used, but part of builtin SPI
int SCLK=13; //sck
void setup()
{
SPI.begin();
pinMode(DATAOUT, OUTPUT);
pinMode(DATAIN, INPUT);
pinMode(SCLK, OUTPUT);
pinMode(ss, OUTPUT); // used for Chip Enable pin
SPI.beginTransaction (SPISettings (100, MSBFIRST, SPI_MODE0)); // our setup requires data to be sent MSB first, frequency 100Hz, mode 0
// Register write bit=,0 Chip Enable bits=01, 5=Reg. Address Bits, 8=Reg. VAlue Bits
// Page Addresses: 3F then 0000 0000
// 0000 Page 0, 0001 Page 1, 0010 Page 2, Page 0011 Page 3, 0100 Page 4, 0101 Page 5, 0110 Page 6, 0111 Page 7, 1000 Page 8
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F00);// Page 0
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0xA023);// Reg 0 Master mode
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x22C4);// Reg 2
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x25E0);// Reg 5
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F02);// Page 2
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3010);//Reg 16 No. of SH intervals and CISb
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F03);// Page 3
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x2002);// Reg. 0 SH 0 state length 200ns
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F05);// Page 5
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x2001);// Reg. 0 SH1 high at 0 state
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F06);// Page 6
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x2000);// Reg. 0 PHIA 2 MSB for duty cycle low
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x2100);// Reg. 1 PHIA 8Bits for duty cycle low
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x2200);// Reg. 2 PHIA 8Bits for duty cycle low
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x231F);// Reg. 3 PHIA 8Bits for duty cycle 3 low 5 high
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x24FF);// Reg. 4 PHIA 8Bits for duty cycle high
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x25FF);// Reg. 5 PHIA 8Bits for duty cycle high
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F08);// Page 8
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x2040);// Reg. 0 PHIA1 active timing
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0x3F00);// Page 0
digitalWrite(ss, HIGH);
delay(5);
digitalWrite(ss, LOW);
SPI.transfer16(0xFFFF);//Dummy Bits
SPI.transfer16(0xA023);// Reg 0 Master mode (PLL & Registers Lock)
digitalWrite(ss, HIGH);
delay(5);
}
void loop()
{
//exit(0);
}
Hi Martin,
Sorry, I could not follow the register write sequence that you've shown.
Can you put the register map into a text format so that it's clear what the register content (Hex value) are?
Regards,
Hooman
Here is the registers configuration that I did, I used Arduino UNO to perform registers configuration via SPI. I used 16+ clock with 4 wires. CE pin is connedted to the VD (CE bits are 01) At first I send 16 Dummy Bits (FFFF) to get 16 clocks and bit values of last configured register and then I send the actual 16 bits for confihuring register. Please have a look on register values data below and let me know where the problem is as soon as possible. #include <SPI.h> int ss=10; // Connected to the SEN pin int DATAOUT=11; //MOSI connected to the SDI int DATAIN=12; //MISO connect with SDO int SCLK=13; // Serial clock void setup() { SPI.begin(); pinMode(DATAOUT, OUTPUT); //register data from Arduino pinMode(DATAIN, INPUT); // values fron LM98725 pinMode(SCLK, OUTPUT); // clock pinMode(ss, OUTPUT); // used for Chip Enable pin SPI.beginTransaction (SPISettings (1000, MSBFIRST, SPI_MODE0)); // our setup requires data to be sent MSB first, frequency 1KHz, mode 0 // Register write bit=,0 Chip Enable bits=01, 5=Reg. Address Bits, 8=Reg. Value Bits // Page Addresses: 3F then 0000 0000 // 0000 Page 0, 0001 Page 1, 0010 Page 2, Page 0011 Page 3, 0100 Page 4, 0101 Page 5, 0110 Page 6, 0111 Page 7, 1000 Page 8 digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F00);// Page 0 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0xA023);// Reg 0 Master mode digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x22C4);// Reg 2 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x25E0);// Reg 5 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F02);// Page 2 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3010);//Reg 16 No. of SH intervals and CISb digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F03);// Page 3 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x2002);// Reg. 0 SH 0 state length 200ns digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F05);// Page 5 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x2001);// Reg. 0 SH1 high at 0 state digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F06);// Page 6 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x2000);// Reg. 0 PHIA 2 MSB for duty cycle low digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x2100);// Reg. 1 PHIA 8Bits for duty cycle low digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x2200);// Reg. 2 PHIA 8Bits for duty cycle low digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x231F);// Reg. 3 PHIA 8Bits for duty cycle 3 low 5 high digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x24FF);// Reg. 4 PHIA 8Bits for duty cycle high digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x25FF);// Reg. 5 PHIA 8Bits for duty cycle high digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F08);// Page 8 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x2040);// Reg. 0 PHIA1 active timing digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0x3F00);// Page 0 digitalWrite(ss, HIGH); delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xFFFF);//Dummy Bits SPI.transfer16(0xA023);// Reg 0 Master mode (PLL & Registers Lock) digitalWrite(ss, HIGH); delay(5); } void loop() { }
Hello Hooman,
In the datasheet on page 87, Figure 66 & 67 shows that the SDI pin is receiving the data commands before the 9th clock but in the description its written that master will take control of SDI pin after the falling edge of the 9th clock.
Secondly I'm also not reading the correct data values of the registers after configuration, I have sent you the register data file and I have also read the register data on oscilloscope but there is one problem when I configure the register 0 on page 0 at the end to lock the register bit and PLL bit but the data I read showed that only register bit is locked and PLL still unlocked.
I send 0hA3 (1010 0011) to lock the registers and PLL but I received 0h23 (0010 0011).
Thank you.
Dear Hooman,
I have read the datasheet again and its written that the master clock source for the CIS sensor will work Crystal Oscillator Mode but in my case I'm not using crystal oscillator. I'm proving a 5MHz CMOS clock to the LM98725 from my FPGA and need 5MHz clock and 1 SH interval for my sensor. Is it possible or it will only work with crystal oscillator.
Thank you
Hi Martin
I've started reviewing your Registers data.txt file and noticed that the Writes you're intending to do to Page 0, Register 0 may actually be Reads. The SPI transfer value sent for those registers is 0xA023.
If I understand your code correctly I think this should be 0x2023.
In fact the first write you do to this address should be 0x2022, to clear the Registers Locked bit and set Master Mode.
Then the final write should be 0x2023 to set the Registers Locked bit.
I'll review the rest of the register values tomorrow and comment further. Please let me know if I've misinterpreted your code regarding the Writes to Page 0 , Register 0..
Best regards,
Jim B
Hi Jim,
Yes you have interpreted it correctly because I was reading the Register 0 at that time but I have tried it with 0x2023 and the result is same. I'm getting the same signal from both PHIA1 and SH1 and not the actual clock. Do I need to configure some other registers also? Please also confirm this that I can get the clock for the sensor from LM98725 while using INCLK for LM98724 from FPGA.
Hi Martin
Your configuration settings (other than Page 0, Register 0) look OK, but I'm not sure the configuration sequence you are using is completely correct.
Please confirm you are now following the required procedure listed in the Operational Setup Sequence in section 7.5.1. The Lock Bit (Page 0, Register 0, Bit 0) must be 0 during most configuration changes. If the Lock Bit is 1, then many key registers are write only. Also please confirm the PLL Locked bit is set (Page 0, Register 0, Bit 7) before changing the Lock Bit to 1.
When all configuration values are set, then change this bit to 1. This should start the line/pixel/sample timing generation in Master Mode.
You can also confirm that all of your register writes are working by reading back those register values.
Best regards,
Jim B
Hi Jim,
Yes I'm configuring the registers as per instructions in the 7.5.1 section. As you can see my first register write command is 0x2022 which means page 0 register 0 bit 0 = 0 and then I configure all other registers. In the end I send 0x2023 but this only locks the register control bit not the PLL bit 7. I have also tried by sending 0x20A3 (which means bit 7 and 0 are 1) to lock PLL and register control bit. But the output is same. I have read all the registers and I got correct values from the chip except for the page 0 register 0. After locking PLL and register control bit (0x20A3) when I read this register (0xA000) it gives me the value which shows PLL not locked only register control bit is locked (0010 0011). I dont know why its not showing PLL locked?
Do I need to lock Register contol bit 0 and PLL bit 7 in two different write commands?
Is it necessary to provide INCLK while writing the registers?
Best Regards,
Martin
Hi Martin
Sorry, I didn't see a write of 22h to Page 0 Register 0. Can you send the updated register write sequence you are using?
Per datasheet section 7.4.25, the input clock should be either stopped or running continuously during SPI writes and reads. And after either starting or stopping the INCLK (or first power-up of the device) the user should wait at least 50ms to allow the internal logic and PLL to stabilize before beginning serial communication.
The PLL Locked bit is a read-only status bit. If it is 0 it means the PLL is not locked. This will be the case of the INCLK is stopped, or if the PLL has not had time to lock to the provided INCLK.
Best regards,
Jim B
Hello Jim,
I have attached an updated Registers configuration file, please have a look. Today I configured the registers with this sequence while +INCLK was applied continuously and I get some sort of clock pulses on the PHIA1 and PHIB1 but its not correct (see images below) because I have set the duty cycle to 50% but the wave form is random. Kindly guide me where is the problem in the registers data or in the circuit. I have also configured the SH1 but didn't get any output from this pin.
One more thing I want to know that when I switch OFF the circuit and turn it ON again, all the registers data get erased and I have to configure all registers again. Is it normal?
Yellow is the INCLK and Blue waveform is the PHIA1 and PHIA2.
digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F00);// Page 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2158);// Reset digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2022);// Reg 0 Master mode digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2140);// Reg 1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x22C4);// Reg 2 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2430);// Reg 4 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x25E0);// Reg 5 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2700);// Reg 7 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F02);// Page 2 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3000);//Reg 16 No. of SH intervals 1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3100);//Reg 17 No. of SH intervals timing x1 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F03);// Page 3 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2040);// Reg. 0 SH 0 state length 200ns digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2100);// Reg. 0 SH 0 state length 200ns digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F05);// Page 5 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2001);// Reg. 0 SH1 high at 0 state digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F06);// Page 6 digitalWrite(ss, HIGH); //delay(5); //set wave form duty cylcle 50% digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2003);// Reg. 0 PHIA 2 MSB=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x21FF);// Reg. 1 PHIA 8Bits=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x22FF);// Reg. 2 PHIA 8Bits=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x23E0);// Reg. 3 PHIA 8Bits for duty cycle 3 high 5 low digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2400);// Reg. 4 PHIA 8Bits for duty cycle low digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2500);// Reg. 5 PHIA 8Bits for duty cycle low digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2600);// Reg. 0 PHIB1 2 MSB=0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF0FF);//Dummy Bits SPI.transfer16(0x2700);// Reg. 1 PHIB 8Bits = 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2800);// Reg. 2 PHIB 8Bits for duty cycle low = 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x291F);// Reg. 3 PHIB 8Bits for duty cycle 3 low=0 5 high=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2AFF);// Reg. 4 PHIB 8Bits for duty cycle high digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2BFF);// Reg. 5 PHIB 8Bits for duty cycle high digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3E00);// Reg. 30 PHIB1 normal timing digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F07);// Page 7 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x20FF);// Page 7 SH1 MSB digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F08);// Page 8 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2040);// Reg. 0 PHIA1 active timing non invert digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2400);// Reg. 0 SH1 active high logic non invert digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2140);// Reg. 0 PHIB active timing non invert digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x28A2);// Reg. 8 TXCLK disabled digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F00);// Page 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x20A2);// Reg 0 (PLL Lock) digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x20A3);// Reg 0 (Registers Lock) digitalWrite(ss, HIGH);
digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F00);// Page 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2158);// Reset digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2022);// Reg 0 Master mode digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2140);// Reg 1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x22C4);// Reg 2 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2430);// Reg 4 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x25E0);// Reg 5 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2700);// Reg 7 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F02);// Page 2 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3000);//Reg 16 No. of SH intervals 1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3100);//Reg 17 No. of SH intervals timing x1 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F03);// Page 3 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2040);// Reg. 0 SH 0 state length 200ns digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2100);// Reg. 0 SH 0 state length 200ns digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F05);// Page 5 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2001);// Reg. 0 SH1 high at 0 state digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F06);// Page 6 digitalWrite(ss, HIGH); //delay(5); //set wave form duty cylcle 50% digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2003);// Reg. 0 PHIA 2 MSB=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x21FF);// Reg. 1 PHIA 8Bits=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x22FF);// Reg. 2 PHIA 8Bits=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x23E0);// Reg. 3 PHIA 8Bits for duty cycle 3 high 5 low digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2400);// Reg. 4 PHIA 8Bits for duty cycle low digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2500);// Reg. 5 PHIA 8Bits for duty cycle low digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2600);// Reg. 0 PHIB1 2 MSB=0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF0FF);//Dummy Bits SPI.transfer16(0x2700);// Reg. 1 PHIB 8Bits = 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2800);// Reg. 2 PHIB 8Bits for duty cycle low = 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x291F);// Reg. 3 PHIB 8Bits for duty cycle 3 low=0 5 high=1 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2AFF);// Reg. 4 PHIB 8Bits for duty cycle high digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2BFF);// Reg. 5 PHIB 8Bits for duty cycle high digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3E00);// Reg. 30 PHIB1 normal timing digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F07);// Page 7 digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x20FF);// Page 7 SH1 MSB digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F08);// Page 8 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2040);// Reg. 0 PHIA1 active timing non invert digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2400);// Reg. 0 SH1 active high logic non invert digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x2140);// Reg. 0 PHIB active timing non invert digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x28A2);// Reg. 8 TXCLK disabled digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x3F00);// Page 0 digitalWrite(ss, HIGH); //delay(5); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x20A2);// Reg 0 (PLL Lock) digitalWrite(ss, HIGH); digitalWrite(ss, LOW); SPI.transfer16(0xF000);//Dummy Bits SPI.transfer16(0x20A3);// Reg 0 (Registers Lock) digitalWrite(ss, HIGH);
Hi Martin
I'm trying to understand what is preventing the PLL Lock Detect bit from being set.
I reviewed your schematic again and I wanted to confirm what logic level you are setting on the /RESET pin of the device. It is connected to M-3. Since this is active-low, this signal should be either floated to allow the built-in pull-up to hold it high, or driven to logic high from whatever it may be connected to. You shouldn't need to apply a RESET signal to the device but it is good to have it available in case it is needed for other debug purpose.
To answer your earlier question, the register settings of the device are volatile. Every time the power is turned off the register values are cleared.
Can you try applying a somewhat faster or slower INCLK signal to see if this has any effect on the PLL Lock bit? I did notice in your oscilloscope images that there is a lot of ringing on the rising edge of the INCLK signal. Is this due to a long ground lead on the oscilloscope probe, or does the signal at the INCLK input really have that much ringing? If the ringing is real that could cause problems. In that case it would be good to add some series termination at whatever is generating the INCLK signal. This will reduce the edge rate and the ringing.
Please let me know the answers to these questions. I'll let you know if I think of any other issues that would prevent the PLL from locking.
Best regards,
Jim B
Hello Jim,
I think the ringing on the rising edge is may be because I'm using passive probes with the oscilloscope. The /Reset pin status is floating, its just connect to a connector M but there is no logic on it because connector is open and not connected to another device.
Today I have tried to run the chip on 2MHz frequency and when I read the register for PLL lock it shows me locked for a while and then again it showed unlock on the same frequency in two consecutive read commands in a loop (see the images). As you can see in the First image PLL lock and Registers lock bits are high (Bit 7 and Bit 0) but in the Second image PLL is LOW again and only Lock bit is high. This happens only once I don't know what causing the PLL lock bit 0.
Hi Martin,
We have used your register settings (file attached) and your clock frequency (5MHz) on the LM98725 and we don't see any problems with PLL lock!
<definition> <reg addr="0" value="A3"/> <reg addr="1" value="40"/> <reg addr="2" value="C4"/> <reg addr="3" value="C0"/> <reg addr="4" value="30"/> <reg addr="5" value="0"/> <reg addr="6" value="0"/> <reg addr="7" value="0"/> <reg addr="8" value="1"/> <reg addr="9" value="D"/> <reg addr="A" value="1"/> <reg addr="B" value="D"/> <reg addr="C" value="1"/> <reg addr="D" value="D"/> <reg addr="E" value="18"/> <reg addr="F" value="24"/> <reg addr="10" value="18"/> <reg addr="11" value="24"/> <reg addr="12" value="18"/> <reg addr="13" value="24"/> <reg addr="14" value="0"/> <reg addr="15" value="0"/> <reg addr="1E" value="0"/> <reg addr="1F" value="0"/> <reg addr="20" value="0"/> <reg addr="21" value="61"/> <reg addr="22" value="61"/> <reg addr="23" value="61"/> <reg addr="24" value="80"/> <reg addr="25" value="0"/> <reg addr="26" value="80"/> <reg addr="27" value="0"/> <reg addr="28" value="80"/> <reg addr="29" value="0"/> <reg addr="2A" value="80"/> <reg addr="2B" value="0"/> <reg addr="2C" value="80"/> <reg addr="2D" value="0"/> <reg addr="2E" value="80"/> <reg addr="2F" value="0"/> <reg addr="30" value="40"/> <reg addr="31" value="40"/> <reg addr="32" value="40"/> <reg addr="33" value="40"/> <reg addr="34" value="40"/> <reg addr="35" value="40"/> <reg addr="36" value="61"/> <reg addr="37" value="61"/> <reg addr="38" value="61"/> <reg addr="3C" value="40"/> <reg addr="3D" value="40"/> <reg addr="3E" value="40"/> <reg addr="3F" value="0"/> <reg addr="40" value="0"/> <reg addr="41" value="10"/> <reg addr="42" value="0"/> <reg addr="43" value="40"/> <reg addr="44" value="43"/> <reg addr="45" value="80"/> <reg addr="46" value="4"/> <reg addr="47" value="C"/> <reg addr="48" value="10"/> <reg addr="49" value="0"/> <reg addr="4A" value="40"/> <reg addr="4B" value="10"/> <reg addr="4C" value="0"/> <reg addr="4D" value="10"/> <reg addr="4E" value="40"/> <reg addr="4F" value="0"/> <reg addr="50" value="0"/> <reg addr="51" value="0"/> <reg addr="52" value="0"/> <reg addr="53" value="0"/> <reg addr="5A" value="0"/> <reg addr="5F" value="0"/> <reg addr="60" value="40"/> <reg addr="61" value="0"/> <reg addr="62" value="0"/> <reg addr="63" value="0"/> <reg addr="64" value="0"/> <reg addr="65" value="0"/> <reg addr="66" value="0"/> <reg addr="67" value="0"/> <reg addr="68" value="0"/> <reg addr="69" value="0"/> <reg addr="6A" value="0"/> <reg addr="6B" value="0"/> <reg addr="6C" value="0"/> <reg addr="6D" value="0"/> <reg addr="6E" value="0"/> <reg addr="6F" value="0"/> <reg addr="70" value="0"/> <reg addr="71" value="0"/> <reg addr="72" value="0"/> <reg addr="73" value="0"/> <reg addr="74" value="0"/> <reg addr="75" value="0"/> <reg addr="76" value="0"/> <reg addr="77" value="0"/> <reg addr="78" value="0"/> <reg addr="79" value="0"/> <reg addr="7A" value="0"/> <reg addr="7B" value="0"/> <reg addr="7C" value="0"/> <reg addr="7D" value="0"/> <reg addr="7E" value="0"/> <reg addr="7F" value="0"/> <reg addr="80" value="0"/> <reg addr="81" value="0"/> <reg addr="82" value="0"/> <reg addr="83" value="0"/> <reg addr="84" value="0"/> <reg addr="85" value="0"/> <reg addr="86" value="0"/> <reg addr="87" value="0"/> <reg addr="88" value="0"/> <reg addr="89" value="0"/> <reg addr="8A" value="0"/> <reg addr="8B" value="0"/> <reg addr="8C" value="0"/> <reg addr="8D" value="0"/> <reg addr="8E" value="0"/> <reg addr="8F" value="0"/> <reg addr="90" value="0"/> <reg addr="91" value="0"/> <reg addr="92" value="0"/> <reg addr="93" value="0"/> <reg addr="94" value="0"/> <reg addr="95" value="0"/> <reg addr="96" value="0"/> <reg addr="97" value="0"/> <reg addr="98" value="0"/> <reg addr="99" value="0"/> <reg addr="9A" value="0"/> <reg addr="9B" value="0"/> <reg addr="9C" value="0"/> <reg addr="9D" value="0"/> <reg addr="9E" value="0"/> <reg addr="9F" value="0"/> <reg addr="A0" value="1"/> <reg addr="A1" value="0"/> <reg addr="A2" value="0"/> <reg addr="A3" value="0"/> <reg addr="A4" value="0"/> <reg addr="A5" value="0"/> <reg addr="A6" value="0"/> <reg addr="A7" value="0"/> <reg addr="A8" value="0"/> <reg addr="A9" value="0"/> <reg addr="AA" value="0"/> <reg addr="AB" value="0"/> <reg addr="AC" value="0"/> <reg addr="AD" value="0"/> <reg addr="AE" value="0"/> <reg addr="AF" value="0"/> <reg addr="B0" value="0"/> <reg addr="B1" value="0"/> <reg addr="B2" value="0"/> <reg addr="B3" value="0"/> <reg addr="B4" value="0"/> <reg addr="B5" value="0"/> <reg addr="B6" value="0"/> <reg addr="B7" value="0"/> <reg addr="B8" value="0"/> <reg addr="B9" value="0"/> <reg addr="BA" value="0"/> <reg addr="BB" value="0"/> <reg addr="BC" value="0"/> <reg addr="BD" value="0"/> <reg addr="BE" value="0"/> <reg addr="BF" value="0"/> <reg addr="C0" value="3"/> <reg addr="C1" value="FF"/> <reg addr="C2" value="FF"/> <reg addr="C3" value="0"/> <reg addr="C4" value="0"/> <reg addr="C5" value="0"/> <reg addr="C6" value="0"/> <reg addr="C7" value="0"/> <reg addr="C8" value="0"/> <reg addr="C9" value="1F"/> <reg addr="CA" value="FF"/> <reg addr="CB" value="FF"/> <reg addr="CC" value="0"/> <reg addr="CD" value="0"/> <reg addr="CE" value="0"/> <reg addr="CF" value="0"/> <reg addr="D0" value="0"/> <reg addr="D1" value="0"/> <reg addr="D2" value="0"/> <reg addr="D3" value="0"/> <reg addr="D4" value="0"/> <reg addr="D5" value="0"/> <reg addr="D6" value="0"/> <reg addr="D7" value="0"/> <reg addr="D8" value="0"/> <reg addr="D9" value="0"/> <reg addr="DA" value="0"/> <reg addr="DB" value="0"/> <reg addr="DC" value="0"/> <reg addr="DD" value="0"/> <reg addr="DE" value="0"/> <reg addr="DF" value="0"/> <reg addr="E0" value="FF"/> <reg addr="E1" value="0"/> <reg addr="E2" value="0"/> <reg addr="E3" value="0"/> <reg addr="E4" value="0"/> <reg addr="E5" value="0"/> <reg addr="E6" value="0"/> <reg addr="E7" value="0"/> <reg addr="E8" value="0"/> <reg addr="E9" value="0"/> <reg addr="EA" value="0"/> <reg addr="EB" value="0"/> <reg addr="EC" value="0"/> <reg addr="ED" value="0"/> <reg addr="EE" value="0"/> <reg addr="EF" value="0"/> <reg addr="F0" value="0"/> <reg addr="F1" value="0"/> <reg addr="F2" value="0"/> <reg addr="F3" value="0"/> <reg addr="F4" value="0"/> <reg addr="F5" value="0"/> <reg addr="F6" value="0"/> <reg addr="F7" value="0"/> <reg addr="F8" value="0"/> <reg addr="F9" value="0"/> <reg addr="FA" value="0"/> <reg addr="FB" value="0"/> <reg addr="FC" value="0"/> <reg addr="FD" value="0"/> <reg addr="FF" value="0"/> <reg addr="100" value="40"/> <reg addr="101" value="40"/> <reg addr="102" value="0"/> <reg addr="103" value="0"/> <reg addr="104" value="0"/> <reg addr="105" value="0"/> <reg addr="106" value="0"/> <reg addr="108" value="A2"/> <reg addr="109" value="0"/> <reg addr="10A" value="0"/> <reg addr="10B" value="0"/> <reg addr="10C" value="0"/> <reg addr="10D" value="0"/> <reg addr="10E" value="0"/> <reg addr="10F" value="0"/> <reg addr="11F" value="0"/> </definition>
We'll next convert our setup to single ended clock (it is currently using LVDS differential clock) to see if we can recreate the PLL not lock that you are experiencing.
I'll keep you posted as to what we find out.
Regards,
Hooman
Hi Hooman,
Today I was working on the project and used 3MHz CMOS clock from FPGA, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation? I have attached both pictures of the clock pulses on the first start without PLL lock and after restart picture.
Blue=output clock pulse
Yellow=SH interval
After restart
My second question is why there's a delay in the clock pulse after the SH interval (Marked in RED).
Hi Hooman,
Today I was working on the project and used 3MHz CMOS clock from FPGA, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation? I have attached both pictures of the clock pulses on the first start without PLL lock and after restart picture.
Blue=output clock pulse
Yellow=SH interval
After restart
My second question is why there's a delay in the clock pulse after the SH interval (Marked in RED).
Hi Hooman,
I want to ask you that how can I configure the SH interval like its shown in the diagram. I'm using SH1 to generate Start Pulse for the sensor but this stops the Clock Pulse. What could be the better solution for generating the Start Pulse withour affecting the clock pulse. See the waveform diagrams that I need to generate SP and CP for the sensor.
Hi Hooman,
Today I was working on the project and used 3MHz CMOS clock from FPGA, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation? I have attached both pictures of the clock pulses on the first start without PLL lock and after restart picture.
Hi Hooman,
Today I was working on the project and used 3MHz CMOS clock from FPGA, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation? I have attached both pictures of the clock pulses on the first start without PLL lock and after restart picture.
Today I used 3MHz CMOS clock, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation?
Hi Martin,
With regard to the clock pulse "skipping a beat" after the SH interval:
This has to do with a need for the LM98725 SH interval (Register page 2, address 10h) to be higher than a minimum or otherwise the HSTG (High Speed Timing Generator) does not get initialized correctly. The system needs to be run for at least 1 line with the SH interval at 12 or greater, and then set the SH interval to 0.
So, here is a procedure that we've found would work. You should follow these steps to see if your problem can be resolved:
1. Set the SH state lengths to at least the minimum (12) and start generating lines.
2. Run it for at least 1 line.
3. Stop generating lines.
4. Set the SH state lengths to 0 for CIS operation.
5. Start generating lines.
This should allow the high speed line timing to get loaded properly and to avoid the glitch in your high speed clock.
To create the signal for the CIS sensor:
You can create the short pulse on one of the SH channels by setting SH1 PIXEL ON at 1 and SH1 PIXEL OFF at 2. This is the signal that can be sent to the your CIS. The detailed timing between this signal and the high speed CLK sent to the CIS sensor can be adjusted by setting the fine timing of the PHIA (or B or C) signals as needed.
Regards,
Hooman