Hi all,
According to the datasheet of AFE5816, FCLK is the same frequency with ADC_CLK.
However my customer reported that the FCLK is a half of ADC_CLK,
and 12bit length of the data to be output are accommodated in one cycle of the FCLK.
It seems that the ADC sampling rate is a half of ADC_CLK.
Is there any divider function for ADC_CLK input?
ADC_CLK:
FCLK:
Regards,
Toshi