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LM98725 - thermal Problems

Christian Mentin
Prodigy 90 points
Other Parts Discussed in Thread: LM98725

Hi everyone,

we are currently developing an Application using 4 of the LM98725. From our first tests we saw that the AFE is getting a bit hot.
We measured TC 80°C (at the case) when running at approximately 35MSPS.
Currently we also have TA 25°C with case open using TTL Outputs. In the real Application TA might rise up to 60°C or still higher, but we can manage that.

What we are really afraid of, is using the LM98725 at 80MSPS, still when the case is open, since then the Case Temperature will rise much more than up to 80°C. My collegue is arguing that we might be actually 10°C above maximum Temperature since in the Datasheet TA is 70°C max. But i believe that in the Datasheet TA is not meaning TC, as well as RJA = RJC + RCA.

We are not using strong drivers at all, since all sensor signals are buffered.
So i also do not believe that we are overloading the LM98725 itself, but the TSSOP Case is just bad in terms of thermal performance and TC is really close to TJ, maybe due to some special packaging?

It would be nice if someone could confirm this thermal behaviour of the LM98725 AFE.
Thanks,

BR Christian

  • 0
    TI__Mastermind 22825 points

    Hi Christian,

    Please refer to the thermal modeling of the LM98725 attached:

    56L TSSOP Simulation.pdf

    The model shows the top of the case being pretty close in temperature to the junction. If you can monitor the top of the package in different conditions, and ensure that the top stays below 110C then it should be OK.

    The temperature you’ve measured on the LM98725 is in-line with what we’d have expected based on simulation results.

    Here are some highlights:

    In the models generated, the case top and die temperatures were within 1 degree C, as shown on page 4 of the file.

    So if you measure the temp at the top of the package with a fairly low thermal load probe you should get a reasonable picture of the die temperature.

    • Theta JA Improvement of 23.2% with 4 layers JEDEC Boards

    – Theta JA with 2 lyrs JEDEC Board: 83.31 (deg. C/W)

    – Theta JA with 4 lyrs JEDEC Board: 63.96 (deg. C/W)

    • Junction temp, Tj Improvement of 17.2% with 4 layers JEDEC Boards

    – Tj with 2 lyrs JEDEC Board: 84.90 (deg. C)

    – Tj with 4 lyrs JEDEC Board: 70.29 (deg. C)

    Based on the “typical” power dissipation of 0.755W in LVDS output mode at the max clock rate (81 MSPS ADC rate) we arrive at a junction temperature of 108 degrees for an ambient temp of 60 deg. C with a 4 layer board (Theta JA = 63.96 deg. C/W.

    Adding multitude of vias from device pin pads to inner layers of the board always help a lot if you can or have already incorporated on your board.

    Regards,

    Hooman

  • 0 in reply to Hooman Hashemi
    Prodigy 90 points

    Dear Hooman,

    This was exactly the information i was looking for! Let me really thank you for perfectly anserwing my question!

    We are using actually a 6Layer Board, but we are just using some few vias for the GND Connections. Since we are also using via plugging, i will try to place as many thermal vias as possible in the upcoming redesign step, since the thermal connection might be a lot better than it actually is, to keep the device as cool as possible.

    Thanks, once more,

    BR Christian

  • 0 in reply to Hooman Hashemi
    Prodigy 90 points
    Dear Hooman,

    one last question maybe. In the simulation there is stated 0m/s airflow.
    So it is assumed that there is no additional airflow, or is it meant that there is no air convection, which will mean the worst case scenario?

    Thanks,
    BR Christian
  • 0 in reply to Christian Mentin
    TI__Mastermind 22825 points

    Hi Christian,

    You are welcome!

    The 0m/s air flow means no forced air (no fan). Natural convection.

    Regards,

    Hooman