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LM98725: Random noise patterns in bias frames

Part Number: LM98725

Hi All,

We are using the LM98725 in a CCD camera (single channel) and are trying to optimise the signal to noise of the output image. The 98725 is running in 2.4 v input mode at 6MHz and we have the internal gain set to minimum for best S/N. The camera works pretty well, but we still have a faint persistent background pattern of random horizontal bands and these are degrading the output significantly. The bands change from image to image and are unaffected by disconnecting the input to the 98725. We have added lots of extra decoupling capacitors to the power rails and bias points, but there seems to be no benefit from these. Having run out of ideas, I am hoping that someone can suggest a fix!

Thanks!

Terry

  • Hello Terry,

    I've contacted the applications engineer who supports this device.

  • Hi Terry,

    I have couple of general questions:

    1) Input is AC coupled in CDS mode?

    2) 2.4V is the peak to peak input signal dynamic range?

    3)That's any significant signal variation over the length of the sensor?

    Thank you,

    Costin

  • Hi Costin,

    1) Yes, it is AC coupled in CDS mode. 

    2) The signal level is adjustable via an external gain control, but is typically about 2v P-P. I have used both 1.2 and 2.4v input settings with similar results.

    3) There is no noticeable gradient across the line length of the sensor - each band is of uniform brightness, if you ignore the read noise.

    Regards,

    Terry

  • Hi Terry,

    Correct me if I misunderstood, are you getting same horizontal bands when inputs are disconnected with same clock?
    Seems to me external noise at the input coming from the board, an FFT of the output may help identify the noise source.

    Regards,
    Costin
  • Hi Costin,

    Yes, if I disconnect the input from the CCD, the bands are more clearly visible - the CCD read noise helps to mask them. It is almost as if the A-D bias offset is randomly shifting by a few LSB. It stays at the new value for multiple lines (random numbers, but typically 10 - 100 lines) and then shifts again. Would a screen shot be helpful?

    Regards,

    Terry

  • Hi Terry,

    How clean is A-D reference(VREFB,VREFT)?

    Another possibility is a timing issue, PLL not working properly. The wait time after INCLK or after soft reset should be 50mS.

    One suggestion is to check page 0 reg0 bit 7-PLL and  bit5 - SH_R. Is SH_R bit set to default 1? a random change may cause this issue.

    Please e-mail me a screen shot at:

    costin.cazana@ti.com

    Thanks,

    Costin

  • Hi Costin,

    The A-D references are only connected to 100n decoupling capacitors and have no other external connections. I did try adding 47uF to each pin, but to no visible effect.

    The lockup time should be no problem, as the system sits in 'expose' mode for long periods after the registers are loaded, but I can check this. I will also check the Page 0 registers, as you suggest.

    I will mail you some screen shots of the effect.

    Thanks!

    Terry