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  • Forum Post: Re: tsw3003

    nancy!
    Hi Yassine, Sorry for the delayed response, it's Spring Break over here [:H] One of our apps folks measured it with a ruler if you just want a rough size, it's 4.5/8 “ x 4.3/4”. The last # is the Header and output end. Also, I have allegro design files but cannot attach them...
    on Mar 19, 2009

  • Forum Post: LVDS output from AFE5808

    WYE HOU LEM
    Hi, I am trying to capture the LVDS data streams and deserialize with Altera's FPGA (Cyclone 4 speed grade C7). I am wondering if LVDS output from AFE5808 has any overhead( like start and stop bits ) per frame of data transmission? Where can i find out more on this information? Thanks...
    on Mar 26, 2011

  • Forum Post: Re: LVDS output from AFE5808

    WYE HOU LEM
    Hi I just bought an AFE5808 evaluation board, and an Altera FPGA, and also the TI's ADC to HSMC bridge. I was hoping to use Altera's FPGA as a high speed deserializer. I know there is a high speed deserializer board based on Xilinx FPGA which is provided by TI, but for some reason i would like...
    on Apr 12, 2011

  • Forum Post: AFE5808 Phase variation

    Andy4678
    Hi, I am looking for a high channel ADC and started looking into the AFE5808. I noticed that the data sheet mentions a channel to channel Phase variation of 11 degree for a 15MHz signal. Looking into other ADCs, I do not see this this parameter at all. Since my application relies on the precise...
    on Jun 20, 2011

  • Forum Post: Re: Is there any sample or resource that deserialises LDVS from AFE58XX and place data for EMIF.

    masatoshi nakashima
    Tanks for your reply. But I am afraid that you do not understand my intent. Sales Engineer in Japan showed a tutorial paper of Xilinx that shows how to interface to EMIF for TI's DSP. We started to study TSW1250EVM(deserializer and Xilinx FPGA sample. If you have other exaple,idea or information...
    on Oct 13, 2011

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