It only indicated Vol SDA and Vol ALERT
What are value when SDA and ALERT Pin goes to high (logic ‘1’) and what is its range?
AT page 9 BUS OVERVIEW:" the device that initiates the transfer is called a master, and the device controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. "
When TMP102 sends data bytes back to the bus, is the TMP102 considered as master or slave? And does it generate clock, start, stop bit?
Generate clock? Or the TMP102 never generate clock signal?
Look the Figure 14, Two-Write Timing Diagram for Read Word Format
Master controls the clock for first two write cycle. When TMP102 send back to master two temperature bytes,does TMP102 control the clock (TMP102 generating the clock signal at SCL line) or still the master has to generate the clock signal.
Does the clock input to the chip need to be 50% duty cycle?
Looked at Figure 14 in datasheet.
SDA and ALERT will be at the rail voltage when they are high (logic 1). The reason is because SDA and ALERT are open collectors and the pull up resistors will pull the output to the rail voltage in the case of logic 1 (high).
The TMP102 will always be the slave device while the microprocessor will always be the master.
The I2C protocol states that the Master is the device which initiates a transfer, generates clock signals and terminates a transfer.
On page 14 you will see the timing diagram. The microprocessor initiates the communication with the TMP102, generates the clock signal (SCL) and tells the TMP102 when to send data. The microprocessor will then end the communication.
I would recommend using a 50% duty cycle. This is the most common and will be easiest to implement.
Best Regards,Chris FeatherstoneLinear Characterization EngineerHigh Performance Linear Products
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