The LM95071 data sheet (SNIS137B) section 1.2 states that the CS signal should be held high for at least one clock cycle (160ns minimum) between communications.
I would like to confirm if this statement means CS should be held high for 1 clock cycle time on the SPI bus so if the SPI clock has a period of 1000ns it should be held high for 1000ns.
Or is the 160ns period fixed (an internal period) and the time CS should be held high between communication can be 160ns even with an SPI clock of 1000ns.
This time does not see to appear in the timing diagrams/table
Regards,
Daniel
Hi Daniel,
It is the second scenario you mentioned and an internal period. Also you need to be aware that since the bus can run at 6/25 MHz that you can aquire data much quicker than a temperature update. It can take a maximum of 228ms for new temperature data to be made available. So if you continously read at a very high rate you will get the same temperature multiple times.
Take care,
Emmy
Integrated Signal Chain ApplicationsTexas Instruments