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TSC2007 POR issue

durmus
Prodigy 40 points
Other Parts Discussed in Thread: TSC2007

Hi,

Having read the app report SBAA161–March 2009 Important Considerations to Assure a Safe POR, I've came up with a few questions.

In Specifications Related to POR section on page 2, it says:

The POR circuit of the TSC2007 contains a capacitor that is charged when the device powers up, and
generates an internal reset signal when the voltage at the capacitor reaches a certain level.

What exactly is this "certain level"?

Also on the same page, it says:

tVDD_OFF time starts when TSC2007 VDD reaches 0V and remains at that level.

How much tolerance is to be expected around 0V? 10mV, 50mV, 100mV or whatever?

I'm asking these questions because sometimes I encounter this POR issue related to TSC2007. I believe the reason might be that when I connect a debugger to my board through a serial port, power supply pin of TSC2007 remain at about 120mV even though the board is not powered. And with this connection, sometimes it starts normally, sometimes not. But when I remove the debugger and power the board on, it always starts normally.

In addition, I must also admit that the power supply I use does not meet the VDD on/off ramp timings for TSC2007. I measured the ramp as 2kV/sec and spec says it must be 12kV/sec at least. But how critical is that actually? Because like I said, I never encountered any POR issue when trying without the debugger.

Thanks in advance.

Durmus

  • 0
    TI__Mastermind 20085 points
    Hello,

    Welcome to E2E, thanks for your interest in our products.
    It is always recommended to follow the given guidelines in the file, if not so, we can't guarantee the device correct behavior. In order to avoid any potential lockup, VDD should meet the requirements for its on/off slope, timing and sequence.

    Best Regards
    Jose Luis Figueroa
    Audio Applications Engineer | LPAA
  • 0 in reply to José Luis
    Prodigy 40 points
    Hi,

    I understand the requirements should be followed but the requirements about the voltage levels are not clear. Hence my first two questions.
    Regarding the third question about voltage on/off slope, datasheet says that these values are not production tested but rather specified by design. Since I did not encounter any problems, I just wanted to state it just in case.
    Still, what I'm actually looking for are the answers to the first two questions.

    Thanks.
    Durmus
  • 0 in reply to durmus
    TI__Mastermind 20085 points
    Durmus,

    Unfortunately, I haven't been able to find the information about the level. But I consider that 120mV shouldn't be an issue, I think that the tolerance should be higher.
    On the other hand, if it is necessary, you could use a circuit how is shown in the Cycle power Circuitry section of the mentioned Application Report in order to resolve this issue.

    Best Regards
    Jose Luis Figueroa
    Audio Applications Engineer | LPAA