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# LM5170-Q1: LM5170-Q1

Part Number: LM5170-Q1

Hallo,

i´m still fighting the problem with loss of accuracy of the set current to the real current.

i always get a deviation of nearly 5% . in Buck mode i have a deviation to the high side which means the real current is higher than the set current, in Boost mode it is the other way, the real current is less than Set current.

In the datasheet i read in the electrical charcteristics a tolerance of the error amplifier at low values of  VCS ( i.e. 10mV) from 49 to 55 at a nominal value of 50 in buck mode. that means the deviation should go in the other direction, because the the error amp would give higher value of VCS to the PWM and it should  regulate the current down. So the deviations should go exactly in the other direction in my understanding.

In boost mode it is the same problem with error amp Tolerance is fro 45 to 51 but current deviation is to minor values.

Can you explain this fact to me?

Thank You

Best regards

A.v. Müller

Dipl. Ing. A. v. Müller

AGIL-Elektronik GmbH

Wittestr. 49

13509 Berlin

Tel.:03043775470

Fax:03043749847

Sitz der Gesellschaft: Berlin

AmtsgerichtCharlottenburg, HRB 83984

USt.ID: 219941214:

Geschäftsführer

Andrea von Müller

Dipl.Ing. Andreas von Müller

### 5 Replies

• Hello Andrea,

First, thank you for using the LM5170.

There are two issues: error in a particular device, and the datasheet EC table limits. The EC table limits are the limits are statistic parameter variations of all LM5170 devices released to the market, and the variations also include the temperature effects. A particular device does usually not vary that much.

For the accuracy, the device is trimmed at production for Vcs=50mV, and checked against test limits at Vcs=10mV. That said, the best accuracy is obtainable for Vcs=50mV. At reduced power (at which Vcs will be smaller), the accuracy is reduced.

To really get a full understanding of your problem, we would like to know your current sense resistor, the load current, and the operating voltage (input and output). Sharing your schematic would help, too.

Best Regards,
Youhao Xi, System and Applications Engineering, BCS Product Line
• In reply to Youhao Xi:

Hallo Xi,

we have an 3mR shunt resistor and i measure with a nominal 3,3V input and a 12V output on HV Port. max  current is 30Amps.

the problem is, that when we first made the design, we had a layout without a uC for giving us the value for iSETA. however the other schematic was as in our second design and we didnot change very much in the power stages: In the first design the current gulation was very good, as the measurement shows.

I attache a spreadsheet with results of our measurements-I measured the voltage on IsetA pin directly , so with our component values it will be nominal 75mV/A aqnd we get a max shunt voltage of 45mV.

The table shows differences between old measurement and measurement of new PCB revision.

It is obviously, that in boost mode the results are worse than in buck mode, but with the first revision it should be okay.

in the second design it seems to be a basically offset in and so the deviation is much greater than in first design. So i think it could be a layout problem although i see only one difference: we had a 4 layer in first design and now there are two additional power layers on pcb.

I give you attached the schematic of the powerstage which does not change fromm first to second revision.

in my opinion it could be either by coupling from the power layers into the CS traces on pcb. But the power copper which lays direct over the CS traces are not "hot". it is the Plus pole  of Elkos on LV port and should be mostly to give better thermal performance. It is not conduct much switch-current, i think .

The layerstack from bottom to top is as follows

Rev1:  bottom (here are the 1R resistors placed)  Inner1( here are the traces from 1r Resistors to CS Pins placed ; each pair is leaded in parallel to the LM5170) Ground , Top ( here are the shunts placed)

Rev2: bottom (here are the 1R resistors placed)  Inner1( here are the traces from 1r Resistors to CS Pins placed ; each pair is leaded in parallel to the LM5170) Ground , Power 1. Power2, Top ( here are the shunts placed)

there is not a very significant difference i think.

Best regards

LM5170_schematic.pdf

Dipl. Ing. A. v. Müller

AGIL-Elektronik GmbH

Wittestr. 49

13509 Berlin

Tel.:03043775470

Fax:03043749847

Sitz der Gesellschaft: Berlin

AmtsgerichtCharlottenburg, HRB 83984

USt.ID: 219941214:

Geschäftsführer

Andrea von Müller

Dipl.Ing. Andreas von Müller

• In reply to Andreas Von Mueller:

Thank you for the schematic, but no spreadsheet was attached...
• In reply to Youhao Xi:

Hallo XI,

i will try it asgain; i also attached layout. Was this in zhe last attachement?

Best regards

Dipl. Ing. A. v. Müller

AGIL-Elektronik GmbH

Wittestr. 49

13509 Berlin

Tel.:03043775470

Fax:03043749847

Sitz der Gesellschaft: Berlin

AmtsgerichtCharlottenburg, HRB 83984

USt.ID: 219941214:

Geschäftsführer

Andrea von Müller

Dipl.Ing. Andreas von Müller

• In reply to Andreas Von Mueller:

Hi Andreas,

I reviewed your layout, which took me awhile in locating and aligning the components and traces. The CS1 traces look good, but the two traces can be placed closer to each other. CS2 traces are not very clear, because I cannot identify which two traces are the pair.

I found your LM5170 IC underpad was not directly connected to the PGND and AGND pin. Would you please refer to Figure 75 of our datasheet, and pay attention to how PGND, AGND and the under pad are connected? There are two arrows showing how the single point ground connections are implemented on PCB. The grounding problem may cause accuracy issues.

I also noticed your R45 =R46 =27k. Since your OSC resistor R35=39k, you basically set your switching frequency to be roughly 100kHz. According to the datasheet equation (14), you should choose R45 = R46 =96k.

Would you please update your layout? If you don't mind, I would like to review your new layout. We can do this via Private Message System.

Thanks,
Youhao