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UC3843: UC3843-based flyback circuit exhibits unstable duty cycle

Part Number: UC3843

I made a flyback circuit based on UC3843.

When the input voltage reaches 40V, the duty cycle is unstable, and the phenomenon is suddenly large and small, which varies between 0.2 and 0.25.

As shown in the figure below, the MOS tube drain source Voltage waveform.

我测试了此时的伯德图,如下图:

At this point, the phase margin is 51 degrees and the gain margin is -33dB. The loop parameters are still quite good.

I don't know what caused this? The loop is stable, but the actual drive wave D is unstable.

  • Hi zoujiangyilang,

    During the idle ring period a resonant process happens during which the magnetizing inductor rings with the Drain node capacitance. The instability that you mention is caused by the turn-on instant catching this idle ring period at different points in its resonance. The result is that the magnetizing inductance starts each cycle from a different initial condition. The duration of the ON period will depend upon this initial condition and will therefore vary from cycle to cycle.

    This issue is normally addressed in Flyback controllers by synchronizing the turn-on instant to the valley minimum. In this case each switching cycle starts from a known initial condition (zero).

    I hope that this answers your question.

    Thanks

    Joe Leisten

  • In reply to Joe Leisten:

    The schematic is shown in the figure above and is based on the reference circuit design given in the UC3843 data sheet.
    I don't quite understand what you said by turning on the control controller to make the power supply turn in the valley. I don't know if the UC3843 has such a function.
    I searched some information on the Internet. Some people said that the current sampling end Isense is unstable due to the influence of clutter. It is recommended that I debug the current-sampling filter resistors R29 and C16 and the current sampling resistor R31.
    I tried to change these three parameters. Indeed, the changes in these three parameters will affect the previously mentioned problem of duty cycle instability. Finally, under a certain set of parameters, the duty cycle is stable.

    But I do not know why this is? I don't know how to design these three parameters. I used the trial and error method to change these three parameters little by little. Fortunately, I debugged it. I don't know how to design these three parameters correctly.

  • In reply to zoujiangyilang:

    Hi zoujiangyilang,
    The UC2843 is a fixed frequency controller and therefore does not have the ability to implement valley switching.
    TI does offer some variable frequency Flyback controllers that implement this feature. Please take a look at UCC2870x parts for this feature.
    Filtering is applied to the ISENSE signal to remove a leading edge spike that occurs around the turn-on transition.
    This leading edge spike will typically cause some very short pulses, when the pulse is terminated by the leading edge spike, and some much longer pulses, when the pulse is terminated by the correct current ramp signal.
    I did not see any evidence of such a large change in duty cycle on the waveform that you presented above? The waveform you showed has much smaller variation in duty cycle and I believe that this is a normal result of not valley switching and should be expected. It will do no harm and the output voltage will be controlled correctly.
    I hope this helps,
    Joe Leisten
  • In reply to Joe Leisten:

    Hello, the UC3843-based flyback power supply I designed is actually an auxiliary power supply for the each chip in the UCD3138-based full-bridge switching power supply.
    During the debugging process, I encountered a confusion.
    When the UC3843-based auxiliary power supply works alone, the full-bridge main power based on the UCD3138 control is unloaded or lightly loaded. The auxiliary power supply is stable and the duty cycle D is also stable.
    When the full-bridge main power band based on UCD3138 is overloaded with 20A-50A, the UC3843-based auxiliary power supply will have the above-mentioned duty cycle instability, so that the ripple of the supply voltage of each chip will become larger, sometimes This will result in unstable main bridge power based on UCD3138 control.
    I don't know why? Is it that the main power is overloaded and interferes with the auxiliary power supply?
  • In reply to zoujiangyilang:

    Hi zoujiangyilang,
    May I suggest you increase the load on the Flyback secondary to see if you can reproduce the issue without the additional complication of the full-bridge. If you can capture the unstable secondary voltage and COMP signal at some level of secondary load it may be easier for us to debug.
    My thinking is that the issue may be related either to the load on the secondary winding, which may increase when the half-bridge is over-loaded. Alternatively the high CM voltage transient applied to the Flyback transformer during over-load my be interfering with normal operation. Hopefully it is not the second option since this may be more difficult to check.
    Thanks
    Joe Leisten
  • In reply to Joe Leisten:

    Thank you.
    I added the load of the flyback auxiliary power supply, so that the full-bridge main power does not work, and it is stable when the flyback auxiliary power supply is loaded separately. If the flyback auxiliary power supply is under no load, there will be instability when the high voltage is input.
    I tried adding slope compensation and added a 100pF capacitor between pins 3 and 4 of the UC3843. As a result, the flyback auxiliary power supply is also stable at full-bridge main power high voltage and heavy load.
    The second case I want to tell you is related to the current loop sampling of the flyback auxiliary power supply. I am also very confused about this. I have seen it in the data before, but the flyback power supply needs to add slope compensation when the low-end heavy-duty CCM mode and the duty ratio D is greater than 0.5. I did not expect this time at the high-end heavy-duty DCM. In the case of a mode with a duty cycle of approximately 0.2, the addition of slope compensation also makes the circuit more stable. I am very confused about this. I am also confused about how the values ​​of R29 and C16 in the current sampling filter section are determined. I often see R29 values ​​of 500 to 1000 ohms, and C16 is often between a few hundred and 1000 pF. I heard that RC is used to filter out spikes when MOS transistors are turned on, but I don't know how to determine R29 and C16. I just tried to change C16, from 100pF to 1000pF, and found that changing C16 does have an effect on the above-mentioned duty cycle D instability.
  • In reply to zoujiangyilang:

    Hi zoujiangyilang,

    Theoretically:

    1) Slope compensation is only required for CCM operation when the duty cycle is greater than 50%.

    2) The external filter capacitor and resistor are only required to eliminate the leading edge spike.

    Actually:

    Inside the controller a simple comparator is used to terminate the pulse when ISENSE pin voltage is equal to the peak current demand. The comparator can easily be tripped early if you have external switching noise spikes added to the ISENSE signal (or GND).

    Even if the spike filtering and slope compensation are not required, they can help in a noisy environment:

    1) The filter helps attenuate externally induced switching edge noise that could otherwise cause the inductor to trip early.

    2) The slope compensation makes the current sense amplitude larger so noise on the signal is unlikely to trip the comparator early.

    Both of these are parasitic benefits that would be difficult to calculate. In a very noisy environment there are advantages to using voltage mode control or average current mode control. Both of these are less susceptible to noise pickup.

    Thanks

    Joe Leisten

  • In reply to Joe Leisten:

    Thank you,Joe.

    I don't know if my understanding is right.
    When the main power is working at the input high voltage and heavy load, noise is generated to the Isence terminal of the auxiliary power supply. When this noise reaches the peak current demand, it affects the turn-on of the auxiliary power supply duty cycle, resulting in unstable duty ratio.
    When I change the filter resistor and capacitor and add slope compensation, the effect of noise on the auxiliary power supply duty cycle is reduced, which stabilizes the duty cycle.
    What do you mean by the noise reaching the peak current, is the noise voltage reaching 1V, which turns off the PWM wave?

    ZJYL
  • In reply to zoujiangyilang:

    Hi zoujiangyilang,

    The controller you are using operates in peak current mode control. This means that the end of each switch ON period is terminated by a comparator detecting that the ISENSE pin voltage has crossed the current demand level. If you have a small spike added to the ISENSE pin voltage from some other part of the system then this spike can cause the duty cycle to end early.

    This has nothing to do with the internal 1V maximum peak current level, which is just the maximum value that can be achieved by the internal COMP level (shown in red below).

    I hope the picture below will help to clarify this process. My theory is that noise from the switching edges of the bridge appears on the ISENSE pin of each Auxiliary supply and causes the duty cycle to become 'unstable'. Adding filtering to this pin or adding slope compensation helps to make it less susceptible to noise, but perhaps using voltage mode control or average current mode control may be a better solutions.

    Thanks

    Joe Leisten

    E2EPicture.docx

  • In reply to Joe Leisten:

    Hi,Joe. I understand it.

    However, the circuit diagram I saw on the UC3843 receipt manual is only peak current controlled.
    Excuse me, do you have a schematic diagram of the UC3843 circuit with voltage and average current control?
    This is convenient for me to imitate the design.

    Thank you.
    ZJYL