Part Number: UCD90320
Hi , This device as well as it's prececessor (UDC90120) do not mention any anti aliasing filter for voltage measurements built inside teh chip or required externally . Monitored voltages will have 5-10 % noise due to switched mode power supplies, what is the rationale behind ommiting this type of filter ?
If it is however implemented what is teh characteristic of this filter ( cut off frequency, order , phase shift, pass band ripple)
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In reply to yihe:
Thank you very much,
I am asking for anti aliasing filter on ADC input for voltage monitoring , since the monitored voltage can be quite noisy ( as it can be from switch mode psu). I found no references to any cap on these inputs?
In reply to Sebastian Ciesluk80:
Sorry for nagging , is there anyone able to help ? Trying to get directly to TI FAE but no success so far.
In reply to Qian Chen:
Hello and thanks for update.
The decoupling can be added but I think it is not related to the aliasing noise from the input of ADC. I guess you talking about sampling capacitor inside teh ADC. Probably he 3dB BW of such a filter is very high so does not filter aliased noise. So how we deal with aliased noise in this device?
Yes, I see now where the filter should go. Even in very well designed PDN systems we will see noise due to ripple or transient load if we supplying complex SoC or Fpga. Fully agree that we can keep adding filters minimising it but it still be there to certain extent and should alias back when sampled.
No I have not done any tests on this device , just thinking how well it would perform as voltage and power monitor.
Hi Sebatian, it is assumed that the supply voltages you intend to monitor are well regulated and free of excessive noise. 10% ripple and noise is way too much for a proper design. Think of the many CMOS-OPAmps which have a maximum supply voltage of 5.5V and are powered with 5V. With 10% ripple and noise you would lose all the safety margin and there would not be any headroom for the supply voltage tolerance. A usual 5V supply can have 5% tolerance. So, ripple and noise should be well under 5%. Also, this application is no analog signal chain, where you are interested in the frequency domain and where you have out of signal band noise you want to reject and prevent from being folded back into the signal band. Here the time domain is relevant. You take a sample at a certain moment and that's it. The ADC conversion rate on each ADC channel is 1MSPS. This is fast enough to prevent any additional error. So, there's no need for a sophisticated anti-aliasing filter. Add the recommended 100nF cap, if your supply is noisy. But that's it. Kai
In reply to kai klaas69:
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