• TI Thinks Resolved

UCC27538: OUTH protection

Part Number: UCC27538

Hi Ti

Is there some internal zener diode connected from OUTH to OUTL in UCC27538? (Similar to D50 in the schematic below)

It seems to pull OUTH down to ~8V, when input goes low, even though OUTL is left unconnected. (In below schematic it happens even though D50 is disconnected)

Can I damage the device by using this zener? (I switch with very low frequency <200Hz, and only charge a few nF through 10ohm)

See schematic below: (VP=21V, VN=0V)

Regards,

Tune

  • Hi Tune,

    Thanks for reaching to the High Power Drivers team, my name is Mamadou Diallo and I will help address your questions.

    The output stage of this device does not have zenner diode, the image below shows the output configuration of the driver.

    The body diodes of the internal MOSFETs at the stage help protect the driver from switching overshoot/undershoot.

    What are you hoping to accomplish with diode D50 on the OUTL pin?

    Also R51 and C37 are really not necessary. Are you trying to implement a filter at the gate?

    When input goes low, the driver's OUTH pin is in high impedance mode since the OUTH and OUTL are not tied together.

    Also you may want to consider increasing C38 to >=1uF as recommended in the datasheet to properly bias the driver and place it very close to the VDD pin for effective noise filter. 

    Thanks in advance for elaborating and I look forward to hearing from you.

    Regards,

    -Mamadou

  • In reply to Mamadou Diallo:

    Hi Mamadou

    Thank you for the quick answer:-)

    I use it to drive a P-channel MOSFET, and D50 is used to ensure that the MOSFET is not turned on durring startup.

    R51 and C37 is used to drive the gate without exceeding the VGS rating.(It cannot take 21V) Notice the MOSFET is turned on when UCC27538 input is low.

    C38: I have more than the 100nF on the VDD PIN, just placed elsewhere on the schematic.

    "When input goes low, the driver's OUTH pin is in high impedance mode since the OUTH and OUTL are not tied together."

    I do not think this is the case, and the reason for my question. I have looked at the datasheet and seen the principal schematic of the output stage. The problem is that OUTH is pulling down to 8V if I leave OUTL not connected.

    Can you ask the design team for more information about this output?

    Regards,

    Tune

  • In reply to Tune Pedersen:

    Hi Tune,

    Thanks for the clarification!

    I will get back to you Monday/Tuesday.

    Thanks for your patience.

    Regards,

    -Mamadou
  • In reply to Mamadou Diallo:

    Hi Tune,

    Thanks for your patience and previous explanation of your circuit.

    I've reached out to my design and I should hear from them by the end of the week.

    In the meantime, (out of curiosity, if possible) can you share application and/or end equipment for this design?

    Also, you specified that VP=21V, VN=0V, What is VZ?

    Regarding the following subject, "When input goes low, the driver's OUTH pin is in high impedance mode since the OUTH and OUTL are not tied together."

    I will refer you to Table 5 (I/O logic truth table) of the datasheet where we specify the driver's output pins behavior:

    Thanks again for your time and patience.

    Regards,

    -Mamadou

  • In reply to Mamadou Diallo:

    Hi Mamadou

    Thank you, looking forward to their response.

    VZ is about 6V, but not important for my question.

    It is for a gatedriver driving large IGBT's.

    Regards,

    Tune

  • In reply to Tune Pedersen:

    Thank you Tune,

    You will hear from me as soon as they get back to me.

    Thanks.

    Regards,

    -Mamadou
  • In reply to Mamadou Diallo:

    I have added some measurement below i just made to understand the output better. I build a small test board, and tried to keep it as simple as possible with a pull up resistor, and also tried with much more capacitive loading than what I have in the real circuit.

    I hope you can provide a more detailed diagram, than what is provided in the datasheet, and tell me if it is safe to use the device this way.

    Looking forward to your response!

    Regards,

    Tune

  • In reply to Tune Pedersen:

    Hi Tune,

    Mamadou is out of the office, so I'll help you with this issue.

    The diagram in the data sheet is accurate.

    It seems to me that you are seeing expected behavior with the way you have the inputs configured, but maybe I don't understand what you're trying to do. Please verify the logic table in the d/s. I don't think you want to tie INH and INL together. I think you need to split them apart to get the output you're desiring.

    Take a look and let me know what you think.

    Best regards,

    Don Dapkus

    Gate Driver Applications Engineering Manager

    Dallas, TX USA

  • In reply to Don Dapkus:

    Hi Don

    "Please verify the logic table in the d/s. I don't think you want to tie INH and INL together."

    According to the datasheet they are called IN1 and IN2 and should follow the truth table given in the datasheet. I Do not understand why I cannot tie them together.

    According to this table OUTH should be high when IN1 and IN2 is high. This is also what i see when i test the device:

    When IN1 and IN2 is Low, OUTH should be high impedance according to the table. This I do not see when I test the device. Please explain to me why OUTH is ~8V when IN1 and IN2 is low. Se below test:

    Regards,

    Tune

  • In reply to Tune Pedersen:

    Hi Tune,

    No worries! You are correct, it's fine to tie IN1 and IN2 together. I misunderstood what you were trying to do.

    In your plots is VDD at 21V?

    Best regards,

    Don Dapkus

    Gate Driver Applications Engineering Manager

    Dallas, TX USA