Part Number: TPS542941
I am using the TPS542941 in the RSA pacakage. I have two questions in regards to using this part:
1 - On the datasheet, p17, it shows a sample layout of this part and i can see that PGNDx is NOT connected to the thermal pad's ground. But on p16 it show the sample layout for the HTSSOP package and the PGNDx IS connected to the thermal pad's ground. Why is there a difference in the connection of PGNDx between the two packages and can you please confirm for the RSA package which i am using, should i follow the datasheet and NOT connect it to the thermal pad ground?
2 - My design is very compact and i am not using this part at the maximum current rating and as such, my inductor is smaller. In the datasheet P17 which shows the sample layout, it suggest that i keep output caps ground vias at least 25mm from the input caps ground vias. I do not have sufficient physical space to do this as my inductor is only 4mm square. Do i still add output cap vias directly below the caps or do i need to move these ground vias so that they are at least 25mm away? Or is this 25mm a typo and should be 25mil (0.025") as in the previous page it inidcates 3-4mm?
1. For the RSA package, please follow the recommendation layout. There is no need to connect the PGNDx to thermal pad.
2. It's recommended that output cap ground vias are kept 25mm from input cap ground vias. If you have limited space, it's OK to have your own layout. You can send your layout to my email firstname.lastname@example.org. I can help to review.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Sam Zhang(MCP):
Ok, i will not connect the PGNDx to the thermal pad. I do think that there is a error in the datasheet, it should read less than 25mil rather than 25mm. I have attached a picture of my layout. I am using three of these in my design and they all look use about the same layout.
In reply to William Sung36:
According to the datasheet layout guidance,
1. The input cap GND vias should be kept >3~4mm from its pad
2. The input cap GND vias should be kept >25mm from output cap GND vias. It's not 25mil. 25mil is just 0.635mm, it's too small.
As your inductor is really small, it's OK to make the distance below 25mm. Please keep them away as far as you can. This is because there is high dI/dt on the input loop, the switching noise may coupled on the output.
One more soft reminder is, please make sure the inductor has enough saturation current rating as it's really small package. Thanks!
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.