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TPS650830: Long press PWRBTNIN to trigger shutdown

Part Number: TPS650830

Hi,

Based on the setting of FLT bits, we can long press PWRBTN to trigger an emergency shutdown.  THe questions are,

  1. After PWRBTNIN is released, how long it takes to finish an emergency shutdown?
  2. Will all the register in UVLO domain be set back to default value from emergency shutdown?
  3. When will the register in RTC domain being reset?

Thanks!

Antony

  • Antony,

    Your question has been assigned to our device expert. He should get back to you soon.

    Thank you,
    Nick Jakse
    --------------------------------------------------
    Find the right power solution for your processor or FPGA. Visit www.ti.com/SoCPower today!

  • Hi Antony,
    The answers to your questions are listed below:
    1. PWRBTNIN release (rising high) doesn't cause an emergency shutdown; only pushing it longer than defined time by FLT[5:0] can cause an emergency shutdown;
    2. Yes.
    3. Only when the RTC domain power rail V3P3A_RTC below the minimum threshold (2V), the RTC registers will be reset to the default values.

    Thanks!
    Phil
    --------------------------------------------------

    For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic 

    Find the right power solution for your processor or FPGA: www.ti.com/SoCPower

  • In reply to Phil Yi48:

    Hi Phil,

    For Q1, what I am asking is, when PWRBTNIN is released after driven low longer than FLT, how much time it takes to recover from emergency shutdown?

    Thanks.

    Antony

  • In reply to Antony Lin:

    Hi,

    The updated question is modified as below.

    Now the customer is doing something as below,

    1. PMIC enter emergency shutdown.
    2. PWRBTNIN is driven low to exit emergency shutdown.
    3. Customer want to configure 0x31 register (under UVLO domain) to a new value,

    The question is, after step2 is done to exit emergency shutdown mode, how long the customer should wait to do step3 to configure 0x31 to a new value?  Customer test to add a 5ms delay, but it seems too short seems 0x31 in the end still be the default value.  But if they tried to add a 3sec, then they can successfully configure 0x31 to the value they want.  So, we need to understand what is the minimum delay required here?

    Thanks!


    Antony

  • In reply to Antony Lin:

    Hi Antony,
    I can't find this data in datasheet. I think, principally, there should be no delay needed, since I2C should be still active during emergency shutdown mode. Please check followings:
    1. if I2C signals are pulled up to VDDIO which should be tied to LDO3V pin = 3.3 V?
    2. When does the "5ms delay" counted from? if it's sure from the PWRBTNIN being driven low (falling edge)?
    If both answers are yes to questions above, can customer try by adding 1mS as step size to get the time? We don't have the software to measure it.

    Thanks!
    Phil
    --------------------------------------------------

    For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic 

    Find the right power solution for your processor or FPGA: www.ti.com/SoCPower

  • In reply to Phil Yi48:

    Hi Antony,
    I've tested on bench EVM; there is no delay needed. The 0x31 register value can be changed even during the emergency shutdown mode, and after exit from emergency shutdown mode by pushing the power button, the changed bits keep as what I want instead of default after reset.

    Thanks!
    Phil
    --------------------------------------------------

    For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic 

    Find the right power solution for your processor or FPGA: www.ti.com/SoCPower