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UCC27714: Design issue

Part Number: UCC27714

Good evening to everyone,

My name is Dario Laezza and I'm an electronic engineering student, with other collegues we are designing a Pre-charge circuit with the IC in the thread's title. Because of the capacitive load (300uF) we have chosen a quite big Bootstrap capacitor (20uF). In order to complete the charge and loose at maximum the 10% of the charge on the Boot capacitor we must modify the 10k resistor placed on the gate of the both switches in the application note. We have read that this resistor is used to avoid a non intentional driving when the IC is not well soldered. My question is: is there any problem if we use a 100k resistor instead of 10k? This help us to loose less charge as possible. Thank you to everyone and good evening.

Best regards

Dario Laezza

  • Hi Dario,

    Thanks for reaching out to the High Power Drivers group, my name is Mamadou Diallo, I am an applications engineer and I will help address your concern.

    You're correct that Rgs is used to provide a path to ground to prevent any false triggering at the gate. The 10k resistor in the datasheet is a typical value of example applications and we use this value as a reference. Not all applications will require Rgs to 10k. The value of this resistor is depending on how fast you're switching (dv/dt) and may be tuned to meet your design requirements. I would suggest starting with 10k first then adjusting the value in certain increments (10k 15k 30k, etc...) to meet your desired goal. How did you determine your 100k value?

    Section 3.5 of this app note does a great discussing how to calculate this resistor: www.ti.com/.../slua618.pdf

    Additionally, you want to size your bootstrap capacitor to be AT LEAST 10x the gate capacitance of your MOSFET(s) as a general rule of thumb. So I would determine the FETs gate capacitance, then sizing your bootstrap cap and your bias capacitor.

    Section 8.2.2.2 of the datasheet (www.ti.com/.../ucc27714.pdf) discusses an approach to ensure that this capacitor is sized appropriately.
    The following app note (www.ti.com/.../slua887.pdf) also discusses several methods to sizing your bootstrap circuitry in your system.

    Please let us know if you have further questions or press the green button if this helped address your concern.

    Regards,

    -Mamadou
  • In reply to Mamadou Diallo:

    Sorry I realized there was a missing link.

    Section 3.5 of this app note does a great job discussing how to calculate this resistor:

    www.ti.com/.../slua618a.pdf

    Please let us know if you have further questions or press the green button if this addressed your inquiry.

    Regards,

    -Mamadou
  • In reply to Mamadou Diallo:

    Hi Mamadou,

    Thank you for the reply. I appreaciated the link you attached but just the last one work. For what concerne the choosen capacitor we follow the calculation on the datasheet but our bootstrap seems to be quite big beacuse of the capacitive load, we take about 200 ms to charge the load capacitor. If we leave the 10k resistor during the high side mos ON time the charge goes down so we simulated the behaviour with a 100k resistor and the lost charge on the boot capacitor is just the 10%. As you could have argued this is not a high frequency application, the load capacitor is charged rarely just before the vehicle's startup. In the notes you attached it talk about the dv/dt turn on, and the dv/dt turn off. Is the first one referred to the maximum Vgs variation? Could we say the fastest drive we can expect? And could you be more explicit when it talk about the turn off and how to calculate the dv/dt for this case? Thank you for the preciuos support.

    Best regards 

    Dario Laezza

  • In reply to Dario Laezza:

    Hi Dario,

    Sorry the links did not work.

     for the component selection guide or here.

    Section 8.2.2.2 of the driver's datasheet found here:

    As for the dv/dt calculations, yes the app note discusses fastest rise at the gate or the fastest drive we can expect. The turn-on dv/dt which is more important because of the presence of dv/dt-induced current. This current can  affect the driver while the gate of the high side FET is high. At turn-off, there is no dv/dt induced current at the gate because this phenomenon often occurs while the high side FET is turning on. What the dv/dt turn-off of the high side FET may cause is negative voltage at the switch node (HS pin) which is an entirely separate issue.

    Please let us know if you have further questions or press the green button if this helped address your inquiry. 

    Regards,

    -Mamadou