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Part Number: UCC27714
Good evening to everyone,
My name is Dario Laezza and I'm an electronic engineering student, with other collegues we are designing a Pre-charge circuit with the IC in the thread's title. Because of the capacitive load (300uF) we have chosen a quite big Bootstrap capacitor (20uF). In order to complete the charge and loose at maximum the 10% of the charge on the Boot capacitor we must modify the 10k resistor placed on the gate of the both switches in the application note. We have read that this resistor is used to avoid a non intentional driving when the IC is not well soldered. My question is: is there any problem if we use a 100k resistor instead of 10k? This help us to loose less charge as possible. Thank you to everyone and good evening.
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In reply to Mamadou Diallo:
Thank you for the reply. I appreaciated the link you attached but just the last one work. For what concerne the choosen capacitor we follow the calculation on the datasheet but our bootstrap seems to be quite big beacuse of the capacitive load, we take about 200 ms to charge the load capacitor. If we leave the 10k resistor during the high side mos ON time the charge goes down so we simulated the behaviour with a 100k resistor and the lost charge on the boot capacitor is just the 10%. As you could have argued this is not a high frequency application, the load capacitor is charged rarely just before the vehicle's startup. In the notes you attached it talk about the dv/dt turn on, and the dv/dt turn off. Is the first one referred to the maximum Vgs variation? Could we say the fastest drive we can expect? And could you be more explicit when it talk about the turn off and how to calculate the dv/dt for this case? Thank you for the preciuos support.
In reply to Dario Laezza:
Sorry the links did not work.
for the component selection guide or here.
Section 18.104.22.168 of the driver's datasheet found here:
As for the dv/dt calculations, yes the app note discusses fastest rise at the gate or the fastest drive we can expect. The turn-on dv/dt which is more important because of the presence of dv/dt-induced current. This current can affect the driver while the gate of the high side FET is high. At turn-off, there is no dv/dt induced current at the gate because this phenomenon often occurs while the high side FET is turning on. What the dv/dt turn-off of the high side FET may cause is negative voltage at the switch node (HS pin) which is an entirely separate issue.
Please let us know if you have further questions or press the green button if this helped address your inquiry.
In reply to BP101:
thank you for the reply but we drive two IGBTs in the Totem Pole and the High Side one provide the current path from the DC bus to the Load Capacitor. We resolved the design issue following the references posted. With a 80k resistor we achive the charging of the capacitor with no problems at all. Moreover we have a very relaxed dv/dt so we avoided the high dv/dt on the output by slowing the high side IGBT turn on. Of course the IC mentioned is not intended for mainly capacitive load but it does the work. Thank you for all the useful replies.
That explains HO was not direct driving 300uf capacitor as 1st post seemed to suggest. We also see somewhat different issues driving inductive load via NFETs and HO dropping >10v during Cboot charge cycles as LO goes low. That sudden drop on HO occurs with 1500nf Cboot and 10uf VDD bias cap via 5.1 ohm resistor to +15v. Luckily HO is near 100v reference to ground, alarming non the less.
Curious if you guys are watching HO signal, trigger source LO and notice similar drop on HO or VDD bias?
So, if I have understood, you noticed a drop on HO when the Cboot charging cycle is completed and LO goes slow to turn off the low side switch. This is quite strange since LO and HO should be indipendent. I'm pretty sure that we did not encouter a problem like this one, but it would be interesting if you could share your schematic, maybe we can analyze it togheter.
It seems the drops HO later shifted to LO (>-10) during HO rise/fall, only after dead band timing was changed from immediate to synchronous update. I agree how does HO or LO effect each other if only via internal creepage. Perhaps HI/LI delay matching (MT) has some kind of effect on both LO/HO outputs under various kinds of modulation. Seemingly Cboot cap was charging in both cases being when LO goes low it dynamically charges Cboot for the next PWM cycle.
Dario LaezzaI'm pretty sure that we did not encouter a problem like this one,
You have to place scope probe on same 1/2 bridge triggering either HO/LO. Issue occurs in resulting wave form near ground with synchronous dead band.
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