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  • TI Thinks Resolved

BQ77915: BQ7791500 AFE chip DSG and CHG MOSFETs not turning ON.

Prodigy 55 points

Replies: 10

Views: 255

Part Number: BQ77915

Hi,

   I'm using the AFE chip BQ7791500 for a 48V BMS system. There are 3 chips cascaded (as per the data sheet connection recommendations) to achieve this configuration. The cell voltages are reaching the ICs and are well within the required range. But the CHG and DSG FETs are OFF (0 V ). As far as I know, the CHG and DSG signals should be high(12V) as per datasheet) , if there are no faults detected by the AFE. The resistors used for setting up fault threshold values are all as per the datasheet recommendations. When the load is connected, the CHG MOSFET's gate shows the total pack voltage wrt battery pack negative (which is extremely high). What could be the issue?. Kindly let me know if any additional changes are needed when we cascade ICs. I'd really appreciate if you could share with me cascaded ICs schematic (for 14S cells specifically) for my reference.

Looking forward to hear from you.

Thanks and Regards,

Bharath B

  • your question will be answered here over the weekday.

    Regards,

    Batt.

  • Hi Bharath,
    Figure 19 of the data sheet shows the OCDP pin of the upper devices connected to the stack ground rather than the local IC VSS as described elsewhere. Be sure you have connected each OCDP resistor to the IC's VSS pin.
    Be sure the wake up circuit is working, the top device PRES pin should be > 1.75V above its VSS. Lower devices will receive the signal from LPWR of the upper device.
    Note the fault conditions in table 5 and consider if there is a fault you have not anticipated. For example be sure the TS circuit for each device is properly connected.
    If PACK- is pulled high the circuit may be in a fault recovery state. Take PACK- low to see if the load removal clears a fault and enables the FET. A circuit like figure 24 of the bq77915 data sheet is typically used, it is common for the charge FET gate to be close to the PACK- voltage in fault.

    TI provides design resources and design advice (including technical, schematic, code and/or system review) “as is” and with all faults.  All information in this or related correspondence is provided subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • In reply to WM5295:

    Hello WM5295, Adding to Mr Bharath's explanation, We have put 300k resistor from OCDP pin to VSS in lower most IC. A 10Mohm resistor is connected from the OCDP pin to VSS for the upper two ICs in the cascaded configuration. Do we have to use exact 294 kΩ±1% resistor as mentioned in the datasheet?. After we made the changes to the circuit as per the above suggestion, the CHG and DSG pins are still at 0V. For the topmost IC, the PRES to Vss( of that IC) is at a voltage of 15.3V. Is this normal?
  • In reply to Subrata Sen:

    Hi Subrata,
    The data sheet does not define the voltage or resistance boundaries for ROCD. Using the recommended value is recommended. An out of tolerance value is not expected to prevent operation of CHG and DSG.
    The current into the PRES pin is very low, see the bq77915 data sheet section 8.6 figure 1. 15.3 V is a suitable voltage to enable the part.
    Some suggestions:
    Be sure each device is on. Check for the presence of AVDD to VSS of each IC. With PRES at 15.3V the top part should certainly be on, the others should be on if LPWR is connected through the appropriate resistor to the PRES of the stack.
    Confirm the top device CTRC and CTRD are connected to the local VSS.
    For the top part, check for DSG and CHG with respect to the local VSS. If they are not high check for fault conditions. Proceed down the stack to the other ICs.
    Note the bq77915 data sheet table 5 for a summary of fault states, FET controls, and recovery conditions. Control of the FETs flows down. The top part should not be able to have OCC or OCD since you have the 10M ROCD on that device and if you have SRN and SRP at the local VSS.
    UTD or OTD will turn off both FETs. Check the connection of the thermistor or resistance, and the RTS_PU. The TS pin is pulsed, it will look like a very low voltage if measured with a meter, observe with a scope to confirm operation.
    With 14S, one device will have 4 cells and the other 5. Be sure the CCFG pin of the 4 cell part is connected to AVDD. If one input is shorted low but the configuration is for more cells, the input will fail OW and both FET outputs will be off.
    If the top part is 5 cells and PRES is connected with a resistor to the top, due to the low current the top part should be powered at about 15.3V. For 5 cells this is 3.06V. For the bq7791500 configuration UV threshold is 2.9V and hysteresis is 400 mV so recovery from UV will not occur until 3.3V. This would not turn off CHG, but may be useful to check if only DSG is off. Raise the applied voltage, or if PRES is controllable in the design, hibernate the part then enable it again. The part will wake in the the UV hysteresis region, and load removal is not required for wake.

    TI provides design resources and design advice (including technical, schematic, code and/or system review) “as is” and with all faults.  All information in this or related correspondence is provided subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • In reply to WM5295:

    Dear WM5295,

    Thank you so much for your inputs.

    We have done adjustments as per your recommendations.

    After changes we have done few measurements, which we want to share.

    Our configuration is 14S, where Lower IC has 5 cells connected, Middle IC has 5 cells and Top IC has 4 cells connected, CCFG Pin of Top IC is connected to AVDD Pin.

    For the top two ICs, the SRP and SRN pins are connected to the local Vss as per the datasheet.

    LD Pin of Top two IC are left floating and for the Bottom IC its connected to Pack Negative though a 10M Resistor.

    We have done some measure

    For the topmost IC, the PRES pin to local IC Vss voltage is 15.62V

    For:

    1) TOP IC: AVdd - local IC Vss voltage is 3.0V

                        CHG pin to local IC Vss is 12.78V

                         DSG pin to local IC Vss is 12.78V

    2) MIDDLE IC: AVdd - local IC Vss voltage is 3.02V

                        CHG pin to local IC Vss is 12.78V

                         DSG pin to local IC Vss is 3.71V

    3) LOWER IC: AVdd - local IC Vss voltage is 3.01V

                        CHG pin to board Vss is 0V

                         DSG pin to board Vss is 0V

    All the cell voltages reaching the IC are above 3.8V.

    We also put the IC to hibernate mode and put it back to Normal mode again. The outputs observed are the same.

    The thermisors used are 103AT. So I guess, UT and OT shouldn't be a problem here.

    Kindly help us to debug the issue.

    Thanks and Regards,

    Subrata

  • In reply to Subrata Sen:

    Hi Subrata,
    When the LD internal pull down is turned on it will be pulled down, otherwise the input will be floating. The paragraph above figure 27 of the data sheet indicates it could be floated if load removal is not used for UV recovery.

    The voltage measurements shown the PRES circuit is working, all the ICs are on.
    The top IC looks correct with CHG and DSG high.
    The middle IC seems to have some damage or improper connection, 3.71V is not a defined level for DSG. It should be driven high or low. Check for missing solder giving a high impedance or some short to another node. You might check the IC pin to see if the level is high.
    You might be sure the IC pins don't wiggle when touched with a probe. Check the DSG pin when probing the input pins to see if DSG goes high indicating a connection, but again 3.7 is not a valid voltage. Since CHG is high there is not apparently an OV, check the VC5 closely.
    Since charge temp control happens first it is not likely a temperature issue. The IC may be damaged.
    The bottom part has both DSG and CHG low. DSG low could be from the upper part voltage being wrong, the CHG low indicates some other issue. Again check the table and eliminate any faults.

    TI provides design resources and design advice (including technical, schematic, code and/or system review) “as is” and with all faults.  All information in this or related correspondence is provided subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • In reply to WM5295:

    Dear WM5295,

    Thank you AGAIN for your inputs.

    We have changed Middle IC

    After changes we have done few measurements, which we want to share.

    LD Pin of Top two IC are left floating and for the Bottom IC its connected to Pack Negative though a 10M Resistor.

    We have done some measure

    For the topmost IC, the PRES pin to local IC Vss voltage is 15.59V

    For:

    1) TOP IC: AVdd - local IC Vss voltage is 0.93V

                        CHG pin to local IC Vss is 0V

                         DSG pin to local IC Vss is 0V

    2) MIDDLE IC: AVdd - local IC Vss voltage is 0.0V

                        CHG pin to local IC Vss is 0V

                         DSG pin to local IC Vss is 0V

    3) LOWER IC: AVdd - local IC Vss voltage is 0V

                        CHG pin to board Vss is 0V

                         DSG pin to board Vss is 0V

    All the cell voltages reaching the IC are above 3.8V.

    We also put the IC to hibernate mode and put it back to Normal mode again. The outputs observed are the same.

    The thermisors used are 103AT. So I guess, UT and OT shouldn't be a problem here.

    output.pdfKindly help us to debug the issue.

    Thanks and Regards,

    Subrata

  • In reply to Subrata Sen:

    Hi Subrata,
    It seems you have moved backward since now the ICs are not ON although U1 PRES is high. The AVdd - Vss3 voltage of 0.93V is abnormal, as if the part is trying to turn on but AVDD3 is shorted to VSS3 or the IC is damaged.
    In the schematic I see many components have capacitors to GND, the battery- or VSS1 potential. When cells are connected or power is applied, the AVDD of U1 will be pulled below its VSS3 by the capacitor CVDD4. A similar thing will happen with VDD, VC1, and VC0. If you bring up a supply slowly I would not expect it to break the part, but suddenly is not known.
    Many nodes have options for zero ohm to GND (battery-) such as R_Zero7, R_Zero26, R_Zero33... . Populating these resistors could damage the attached IC.
    You have the board and will be best able to measure, test, and modify it.
    U2 appears to be at GND/battery- and has the partterns to provide GND connections at the VSS of the part. It may be easy to populate the resistors to use the part standalone and get accustomed to working with the part before re-connecting and working with the upper devices. Again I would not expect the capacitors to battery- to break the part if used with a power supply and cell simulation resistors, but it would likely cause problems with real cells and system transients.

    TI provides design resources and design advice (including technical, schematic, code and/or system review) “as is” and with all faults.  All information in this or related correspondence is provided subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • In reply to WM5295:

    Dear WM5295,

    We failed to mention a point in the previous post. The Avdd - Vss of the IC U1 was initially at 2.97V soon after cell taps connection. But after 2 -3 seconds, it gradually started falling down and leveled out at 0.93 V.

    Regards,

    Subrata

  • In reply to Subrata Sen:

    Hi Subrata,
    It sounds like something is floating or coupled by a capacitance.

    TI provides design resources and design advice (including technical, schematic, code and/or system review) “as is” and with all faults.  All information in this or related correspondence is provided subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

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