Part Number: TPS780
The TPS780 data sheet curves for ground pin current versus input voltage always stop at a minimum Vin well above Vout. What happens to quiescent current in the vicinity of Vin? Do you have any curves which show ground pin current for Vin = 5.2V down to zero, rather than stopping well above dropout voltage?
Your data sheet Electrical Characteristics similarly only spec ground pin current for Vin > 0.5V above Vout.
We need to know the quiescent current for Vin in the vicinity of Vdropout at approximately zero output current.
In reply to JCHK:
Thank you for this valuable information. While 5 uA is a little high, I think we can live with it during low battery. That just about resolves my issue, but before closing this out I have one more question, from earlier, regarding the TPS7A02:
I saw in the preliminary TPS7A02 data sheet that there is a maximum spec of 22uF on the output cap -- the spec says Cout must be in a range between 1 uF and 22 uF. Most regulators I have seen do not have a maximum spec on Cout, they only have a minimum capacitance and a max ESR spec. Could you verify that the TPS7A02 in fact requires that Cout not be over 22 uF? This could easily happen when adding up all the ceramic capacitors across the board (in parallel), or if there is a low-ESR electrolytic somewhere on the output .
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In reply to Engineer1:
The reason for the maximum capacitor at COUT is for a couple of reasons.
1. Above 22uF to 100uF, the LDO may take longer to stabilize after a load transition. This could be mitigated by adding a <1Ohm resistance in series. But given most applications we are targeting for this part are space-constrained, we do not plan on recommending this in the datasheet.
2. As you increase the size of COUT, you also increase the leakage, This may actually be larger than our Iq.
3. If COUT is very large, during startup, we might go into its current limit which would make the startup profile non-monotonic. If the VIN-VOUT delta is large, it may go in and out of thermal shutdown.
Is there a reason that you would like to add more than 22uF at COUT?
Let me know,
John Cummings 蔣康明Texas Instruments 德洲儀器Johncummings@ti.com
Please click the "Resolved" link at the bottom of this post if I have answered your question.
Thank you for this thorough explanation.
Taking longer to stabilize after a transition is not a problem as long as it does not start oscillating.
Leakage (in the 'lytic) could be higher than Iq for the first 24 hours or so, but lower after that.
A longer or non-monotonic startup is not an issue -- if it goes into current limit for a fraction of a second when input voltage is applied that's OK.
We have zero to 100 mA current pulses regularly occurring, trise < 1 usec, faster than any regulator can react.
It sounds like the TPSA02 will not go unstable if a large low-ESR cap is on the output, is that correct?
We have only simulated up to 100uF. The device was not unstable, it just took a bit longer to recover. These are fairily ideal simulations in that they do model the ESR of a typical capacitor, but they do not take into account contact resistance and PCB trace resistance which would help with stability. How large of a capacitor were you planning on using? I can see if we can get a simulation done.
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