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TINA/Spice/LMG5200: Unintended turn-on of the LS-FET during intended turn-on of the HS-FET

Part Number: LMG5200

Tool/software: TINA-TI or Spice Models

Dear community,

I am willing to use the LMG5200 half bridge IC with integrated GaN-FET drivers in a buck converter setup. Therefore, I have simulated the circuit in PSpice with the available simulation model of the LMG5200 and I came across a circuit behavior I did not expect. When the HS-FET turns on after the adjusted dead time (10 ns), an unintended turn-on of the LS-FET occurs, which leads to a shoot trough from V_IN to GND. The attached picture shows the voltage of the switch node voltage V(U1:SW) in the upper graph, and the two currents I(U1:VIN) and I(U1:PGND) in the lower graph present the current flowing through the HS-FET and LS-FET, respectively. Note that I(U1:PGND) is the current flowing from source to drain of the LS-FET and that the current spikes are clipped in the picture (the current peaks up to 35 A in the HS-FET).

Is this just a problem with the simulation model or is there no internal circuitry in the device that prevents the LS-FET from turning on during the rising transition of the switch node voltage? I assumed that the internal driver behaves like the LMG1205 GaN-FET driver (or similar) which is explicitly capable of preventing unintended turn-on.

Best regards,

Maximilian Grams

  • Hello Maximilian,

    Thanks for your question.

    As you can see that there is a shoot through on the upper and lower FET. For LMG5200:

    1. The driver of LMG5200, as well as LMG1205 and LM5113 do not have shoot-through prevention function, which means it allows the upper and lower FETs to be turned on at the same time. The two PWMs are independently controlled.

    2. Could you show me the input PWM signals (HI and LI) and zoom in at the dead time please? Looks to me the real deadtime that goes into the IC may not be 10ns. The shoot through is quite short, which is around 3ns. Could you also increase the dead time and have a try?

    Thanks and regards,
  • In reply to Lixing Fu:

    Hello Lixing,

    Thank you for your fast reply.

    I am aware of the fact that there is no internal "security function" which forbids both FETs to be turned on simultaneously by the PWM signals. As you already mentioned (and as stated in the data sheet of the LMG5200), the two input signals are independently controlled.

    First of all, you are absolutely right regarding the dead time. The picture in my first post shows the simulation results for a dead time of 20 ns, I have accidentally mixed-up the screenshots. Nevertheless, neither a dead time of 10 ns nor 30 ns solves the problem with the shoot through. Please note that the visible dead times in the graph of the switch node voltage differ, as the fall time is approximately three times longer than the rise time.

    In the picture attached you can see that there clearly is a fixed dead time of 20 ns between the transitions of the HI and LI signals. Therefore, there should be no problem with inadequate timed control signals. Please note the propagation delay (approx. 35 ns) of the driver stage.

    In my opinion, the partial shoot through occurs because of the so-called "Miller turn-on". As the voltage at the switch node rises from 0 V to 50 V in less than 2 ns, the capacitances of the (switched off) lower FET charge very quickly. If the driver does not provide a parallel current path across the gate source capacitance C_GS, the voltage V_GS could rise above the threshold voltage V_th. The consequence would be an unintended turn-on of the lower FET due to the switching action of the upper FET.

    Referring to my first post, it would be great to know whether the driver of the LMG5200 includes such a parallel current path (or any other implementation) to actively prevent this kind of unintended turn-on. As far as I understand from its data sheet, the LMG1205 gate driver includes such a protection mechanism: "In addition, the strong sink capability of the LMG1205 maintains the gate in the low state, preventing unintended turnon during switching."

    Best regards,


  • In reply to Maximilian Grams:

    Hi Maximilian,

    The driver in the LMG5200 is very much like the LMG1205 driver and it does have a strong sink capability to keep the fet off and resist miller turn-on. The current you are seeing could have one of two explanations. Either the spice model is incorrect and is suffering from miller-induced turn-on (once again, in the real device, this will not happen but may be the model is in error) or the current you are seeing is the normal Fet-Coss charging current. As this edge is the hard switched edge, when the fet turns on it is normal for the current to surge well above the load current for a time during which excess current is used to charge and discharge the fet Coss capacitance. However, this current surge looks higher than I would expect for that purpose so it merits further investigation. Lixing or I will attempt to re-produce this waveform with our internal un-encrypted spice model and get back to you on what is causing this surge of current.



  • In reply to Nathan Schemm:

    Hello Nathan,

    Thank you for your very helpful answer. It is pleasant to hear that the driver in the LMG5200 is comparable with the LMG1205. Until you or Lixing get back in contact with me, I will mark your feedback as the solution for my problem. Thank you both for all the effort!

    Looking forward to hearing from you,


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