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[FAQ] TLV733P: ESR and load cap restriction to keep stable operation

Part Number: TLV733P

Hi Team,

One quick question.

How large cap and its ESR is allowed as Cout for TLV733?

Fundamentally, that's information is important to keep its output stable for P type LDO but there is no description in datasheet. 
Or N-DMOS architecture is used for TLV733 also, which is described in the following app note?

http://www.ti.com/lit/ml/sbvy001/sbvy001.pdf


Regards,

Takashi Onawa

  • Hi Takashi,

    As a capacitor free design, TLV733P was designed for applications that use small ceramic capacitors or no capacitor at all.  While we do recommend a 1 uF ceramic capacitor or larger for improved ac performance (PSRR, transient performance, etc), we recommend that the output capacitance should not exceed 100 uF.  As TLV733P was designed for ceramic capacitors low ESR is not an issue.  The upper limit on ESR is set by the ESR zero (1 / (2 x pi x ESR x Cout)).  For a stable system you want to make sure that the ESR zero is outside of the bandwidth of the LDO.  For TLV733P, make sure that the ESR zero is beyond 10 kHz.

    As with any linear regulator, we recommend performing worst case load transient tests while monitoring the output voltage on a scope to determine if your selected capacitor is adequate for your application.  The EVM can be used to help with this prototype test.

    Very Respectfully,

    Ryan

  • In reply to Ryan Eslinger:

    Hi Ryan-san,

    Thanks, I understood.


    Regards,
    Takashi Onawa