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LM5119: Customer design error resulting in device failure

Part Number: LM5119

Hi,

I am using an LM5119 to produce a single output (i.e. interleaved operation), circuit attached.  The input voltage spec is 24 - 65V, the output voltage is variable from ~5 to 12V, set by an external DAC feeding into the FB node via a 2.2k resistor.  The circuit generally works well, has good output current capability, accurate output voltage across the full range, tolerates a short circuit, works across the full input voltage range.

The problem I am seeing is occasional catastrophic device failure. Flash of light from the LM5119 followed by small puff of smoke and the LM5119 is no more.  No other device in the circuit seems to be damaged during the failure, although I did have a high-side FET die simultaneously on one occasion.  I do not believe this has anything to do with the LM5119; it is entirely my fault but I'm not sure what is causing the failure because it happens unpredictably and also quite fast.  I did provoke this failure on one occasion by making a DAC output have a step change from 4 to 0V.  This should have caused the corresponding output voltage to go from 4 to 12V, but instead the IC blew.

I should add that this circuit is one of many largely identical circuits powered from a common HV bus.  They have clocks that are synchronised but phase offset from each other to spread the current draw evenly across time.  There is a total of 160uF of ceramic (X7R) capacitance on the HV bus.  There is also a 60V TVS, doing pretty much nothing it would seem.

Do you have any thoughts on what might be causing my LM5119s to blow?Servo Switcher-Servo A Switcher.pdf

Kind regards,
Andrew

  • Hi Andrew,

    Do you know the Vin and Iout condition when the failure happened? Below is my thought.

    1.  LM5119 Vin rate is 65V. If your input voltage is up to 65V, the transient Vin voltage during switching may exceed 65V and damage the IC.

    2. Another possibility is the high voltage spike on switching node. Can you check use oscilloscope probe to check SW voltage spike?

    3. LM5119 internal LDO is used to supply gate drive circuit. When VIN is high, the power loss on IC could be large. Can you check if the IC temperature is very high at high Vin condition?

    4. If the failiure happens during Vout transition, can you slow down the transition slew rate and see if the failiure is related to Vout slew rate?

    Thanks

    Qian

  • In reply to Qian Chen:

    Hi Qian,
    Thank you very much for your helpful thoughts.

    Vin was above 42V when I have noticed the failure. I do not think it has happened with lower input voltage, but I can't be 100% sure. It has occurred with and without a load.

    1. I scoped the HV supply rail (Vin) at various voltages and loads. Spikes are at most +2V above nominal. It looks surprisingly clean for a common switcher rail.
    2. Yes! The SW node ringing at Vin=40V is at +68V. It is somewhat load dependent. At Vin=50 the SW node ringing goes up to +80V. I did not try Vin=65V because it is clearly going to be excessive. This is almost certainly the cause of my failures.
    3. The LM5119 IC is warm but not hot. I provide +12V to both high side gate drivers via diodes from a separate 12V supply, so the internal LDO regulators should not be doing any work.
    4. Good idea. I will plan on slew rate limiting any output voltage changes, just to be on the safe side, but I think item 2 is probably what is causing the failures.

    I have experimented with the snubber and I can reduce the ringing on the SW node, although the price is increased power dissipation in the snubber. A series combination of 3.3nF and 10Ohms gives reasonable results without too much power loss. Larger capacitor values work better at reducing the ringing, but the resistor power dissipation goes up alarmingly.

    I will also look into a gate or bootstrap resistor to slow down the turn on of the high-side FETs. Do you have any value suggestions?

    Kind regards,
    Andrew
  • In reply to Andrew Dunlop:

    Further experimenting with snubber values gets me another 30% reduction in the overshoot on the SW node. I now have a 1 Ohm resistor with a 3.3nF cap in series. Power dissipation in the snubber didn't change too much (it seems to be mainly dependent on the capacitor value), but I will increase the resistor's power rating up to 0.5W to be on the safe side.

    I am now only marginally outside the device limit of 75V under worst-case conditions, so hopefully adding a bootstrap resistor or ferrite will get me inside the device limits without too much more of an efficiency penalty.
  • In reply to Andrew Dunlop:

    Hi Andrew,

    Thanks for the udpate.
    I suggest to use boot resistor to slow down the turn-on of high-side FET and reduce voltage spike on switching node.


    Thanks
    Qian
  • In reply to Qian Chen:

    Thank you very much for your help!

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