TI Thinks Resolved

TPS659039-Q1: power sequency

Dongbao Zhou

Hi team,

My customer has some questions about the power sequence of tps659039, please help check:

1. Xi-osc0 powers up 6.6ms ahead of vddshv8, which is different from the required power sequence? Is there any risk and how to improve?

2. Similar issue for vdda-rtc and vdda-abe-per, the actual test show that vdda-abe-per is 0.58ms ahead of vdda-rtc.

OTP version is O9039A387IZWSRQ1. Thanks

Dongbao

Expert 5010 points

Krishnamurthy Hegde
- Oct 15, 2018 7:28 AM
Hi,

I have assigned your request to responsible Applications Engineer and we will get back to you as soon as possible.

Regards,

Murthy

Find the right power solution for your processor or FPGA. Visit www.ti.com/SoCPower today!
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Intellectual 1610 points

Dongbao Zhou
- Oct 15, 2018 12:13 PM
Another quesiton is, is there any requirement for the power supply sequence of tps659039? 5V is used to power LDO7_LDOUSB_IN, LDOUSB_IN2 and LDO12_IN, 3.3V is used to power the rest LDO and buck. Any timing requirement for 5V and 3.3V?
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Expert 4290 points

Nastasha
- Oct 15, 2018 2:06 PM
In reply to Dongbao Zhou:
Dongbao,

Hi, hope you are doing well. The 5V and 3.3V supplies should be high before the power sequence starts. It does not matter in which order they come up. If they don't come up before the power sequences begins, the SMPS and LDO rails may show a false short-circuit detection.

On your sequencing questions, I think you are referring to the VRTC of the TPS659039-Q1? This rail is always-on and expected to be high ~6ms before the OTP power sequence begins. If the customer is following the platform connection of the TPS659039-Q1 to the AM57xx processor, there should not be any issues with the power up sequence timing. (User Guide: www.ti.com/.../swcu175c.pdf)

Please let me know if this answers your questions.

Thanks,
Nastasha

--------------------------------------------------
For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic

Find the right power solution for your processor or FPGA: www.ti.com/SoCPower
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Intellectual 1610 points

Dongbao Zhou
- Oct 15, 2018 3:43 PM
In reply to Nastasha:

Hi Nastasha,

Thanks for your reply.

I just upload the wrong one for the first picture, i am sure they follow the recommendation, and it has no problem for the processor. However, the test results have some difference.

Dongbao
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Expert 4290 points

Nastasha
- Oct 15, 2018 3:54 PM
In reply to Dongbao Zhou:
Dongbao,

I am not sure which processor the customer is using so I do not know if there is any risk here. Can you ask this question on the processor forum? The processor team will have better understanding of whether there is risk to the processor. Please let me know if you have any PMIC concerns. If not, I will close this thread.

Thanks,
Nastasha

--------------------------------------------------
For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic

Find the right power solution for your processor or FPGA: www.ti.com/SoCPower
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Prodigy 120 points

FENG XIAOYU
- Oct 16, 2018 2:39 AM
In reply to Nastasha:

As described in the DATASHEET: xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown

The crystal signal xi_osc0 is controlled by the PMIC input power supply vdda_osc, but as the power-up sequence in DATASHEET，xi_osc0 is delayed after a long time after vdda_osc is turned on.

Our measured results are the same, so we want to know if it is necessary to design consistent with DATASHEET?
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Expert 4290 points

Nastasha
- Oct 16, 2018 2:05 PM
In reply to FENG XIAOYU:

Feng,

This is not part of the TPS659039-Q1 datasheet. I am moving this thread to the processor forum.

Thanks,

Nastasha

--------------------------------------------------
For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic

Find the right power solution for your processor or FPGA: www.ti.com/SoCPower
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question
Genius 11210 points

Stanislav Stilyanov
- Oct 16, 2018 2:57 PM
In reply to FENG XIAOYU:
Hi Feng,
Think of the moment when clock starts on the diagram as the last moment allowed. Earlier start is allowed provided vdda_osc is present at that time. The PMIC should be already handling this.
If clock is via crystal on XO and XI pins, then user cannot control clock start either.
At last but not least, let's don't forget that clock oscillators need some time to stabilize at the required frequency, they don't start instantly.

Regards,
Stan
- Locked
- Cancel
Do you have another question?

We are glad that we were able to resolve this issue, and will now proceed to close this thread.

If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.

Ask a related question Ask a new question