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TPS659037: Max capacitance loading value

Part Number: TPS659037
Other Parts Discussed in Thread: AM5728,

Hi, There is spec for each phase of SMPS output: the max capacitance loading is 57uF per phase which including PMIC output capacitor and all the capacitors on the loading. 

I noticed in AM5728 GP EVM design also IDK EVM design, they use SMPS 3 for VDD_DDR power rail(input 3.3V, output 1.35V), the total capacitance load is exceeding 57uF far away( roughly 150uF something). Both the two design is using single SMPS 3 output because the current demand is sufficient for DDR power requirement. However due to massive decoupling capacitors required by not only CPU DDR power pin, but also DDR chip power pins, it is not possible to constrain the total capacitance below 57uF.

Is it OK to design like this? 

Also, there is application note "TPS659037 Operation With Higher Capacitive Loading", in which it seems only allow 90uF for single phase:

Based on the performed tests, single-phase rails could support up to 90-µF total capacitive loading (COUT of the SMPS plus all decoupling at the point of load) at a 3.3-V supply and a minimum output voltage of 1V.