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TPS61030: Internal short between SW and GND

Part Number: TPS61030

Hi,

I'm using the TPS61030 to boost a lipo battery up to 5v. So far, I've made four test boards.

Board 1: this one works fine.

Board 2: this board always returns the input voltage minus 0.4v I posted this earlier and was suggested that it could be a bad device. I decided to make two more to test.

Board 3 and 4: These boards failed on first power up. This time, the failure was an internal short in the IC between SW (pin 1 and 2) and GND (pins 3, 4, and 5). No short between SW and PowerPad. After determining this, I replaced both with fresh ICs and they seem to be functioning as expected. I thought, maybe damage during reflow (though temperature was within datasheet spec).

However after a short while in the field, board 1 (which was working) failed in the same way boards 3 and 4 initially did: an internal short between SW and GND.

So currently I only have 2 out of 4 devices working. I had planned to make more, but am now a bit uncertain.

Further searching yields these two posts which show the same issue, but without a real solution:
http://e2e.ti.com/support/power-management/f/196/t/210090

http://e2e.ti.com/support/power-management/f/196/p/678739/2505615


My layout has posted and edited slightly with suggestions from this forum, but still curious as to what the issue could be and welcome any suggestions on how to prevent it.

Original post if helpful: https://e2e.ti.com/support/power-management/f/196/t/730044

I've attached my updated layout and schematic.

Tim

  • Hi Tim,

     I suggest you could test SW waveform using a good board. I think because SW spike is high to broken the device. You could add RC snubber to fix it.

     You need to use short ground probe to test.

      

  • Hi Jing Ji,

    Unfortunately, I don't have access at the moment to an oscilloscope (will try to get one in the future), though I do plan to try (based on available space) adding unpopulated footprints for snubber circuit to experiment later.

    I guess this means the layout itself is generally okay though?

    Would it also make a difference if I ramped up the load (~1-2A+) gradually over a 1-2 seconds instead of all at once?

    Tim

  • Hi Tim,

     There is a problem about layout. Input cap should close to Vin and IC GND pin. And you should put some vias at input cap GND pad.

      Normally, SW spike is related to Iout.The higher Iout, the worse SW spike.

  • Hi Jing Ji,

    Thanks for your suggestions. I've modified the layout accordingly and added a snub circuit (though they'll be left unpopulated if it turns out it is not needed). Any new thoughts?

    Tim

  • Hi Tim,

      It looks better. If you could remove vias place like the picture, it will be better. Because vias in the power trace will insert some noise.


  • Hi Jing Ji,

    Okay. I've made the changes. Not sure if it'll solve the original issue, but going to get some more prototypes made and see. Will post a new question if the issue arises again.

    Thanks for your help and suggestions.

    Tim