Other Parts Discussed in Thread: SN74LVC2G126, CSD
Hi,
I'm planning to incorporate CSD95379Q3M in a half bridge push pull design (a half bridge on primary side, and output without inductor). This design has intrinsic ZVS behavior, which saves power.
However, to achieve ZVS, it must operate with considerable amount of dead time between high drive and low drive.
To implement this feature, I need some data from TI:
1. What's the switching node capacitance (Cds_hs+Cds_ls) at 5V Vbus?
2. How can I control the dead time?
So far, my plan was to use the tri-state to trigger a dead time using 2 PWM signals, one for tri-state driver OE, the other for real PWM signal. That should give a 3-level signal.
Another question is on the SKIP pin. I would like to have it floated when I don't need it, so I can save some 122uA of current at idle. However, is there a guideline on how to implement very low power sleep mode? I noticed the datasheet saying do not float SKIP during power up, so how I'm supposed to float it?
I can drive SKIP pin with a tri-state-able MCU pin, but at power up, MCU pins are all tri-stated, so SKIP will be floating. I can only drive SKIP high or low after MCU boot up, which takes time. How should I connect this pin?
To be clear, the behavior I want is that the chip does very low power when I enter sleep, and they chip goes to FCCM when I want it to run.
Thanks,
B.G.