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LM5176: Layout clarifications

Part Number: LM5176
Other Parts Discussed in Thread: LM5175

G'day,

I'm using an LM5176PWPT to provide a 12V rail for my device from a 7-27V input. I've read through the datasheet a number of times, and have used the Webench tool to construct a suitable schematic. I've followed the layout guidelines presented in the datasheet, which has resulted in the below rough draft:

Without the top layer fill so you can see the individual components:

A couple of notes:

  1. The outside yellow line is the edge cut of the PCB
  2. The outside white border is the 2mm keep out
  3. This is a 4 layer board (signal, GND, PWR, signal); red is top signal, green is bottom signal, pink is PWR.
  4. U26 is the LM5176, shown on the reverse side of the board (top right corner); I obviously haven't yet routed anything to/from it.

The datasheet shows the LM5176 being placed on a large ground fill. As my power circuitry is at the bottom of my board, I'm somewhat pressed for space, so can't have the LM5176 on the same/top side of the board as the datasheet suggests. My question is as follows: if I use a ground fill on the reverse side of the board, and make the required connections to the top ground fill as well as the solid GND plane (layer 2) with vias, can I place the LM5176 on the reverse side of the board, directly underneath the MOSFETs, inductors, etc.?

  • Hi Jars121,

    the engineer supporting this device is out of office and the post is assigned to him. He will reply your question after back to office.
  • Hi Jasper,

    Thank you for letting me know. Any chance you know roughly when they will be back in office?

    Thanks!
  • Hi Jars,

    The layout of the power train components (Inductor, MOSFETs, capacitors...) looks good.

    It is okay to place the LM5176 on the back side of the board. Please just try to minimize the trace lengths. The GND plan is around the device is used to help keep the IC cool.

    I would suggest slightly offsetting the LM5176 to position it below the current sense resistor. This should help to keep the noise seen by the IC to a minimum. I also recommend having and internal ground plane to shield the LM5176 from high noise signals.

    Please let me know if you have any questions.

    Thanks,

    Garrett
  • Hi Garret,

    Thank you for your input, it is greatly appreciated. I will try and keep the trace lengths on the back side of the board as short as possible; I understand that the GND fill and plane is used as a heatsink for the IC.

    In terms of offset, is the current sense resistor the resistor with the Kelvin connections (as per the datasheet)? If so, my Rsense is R251 (in the screenshots in my original post), which is at the bottom of the board; how would you advise I place the IC given the resistor's location? Secondly, are the Kelvin connections I've started on R251 suitable? Given the space between pads on the chosen resistor, I can't route from the centre of the pads, so will start the routing from the right-hand edges. I will route them as a pseudo-differential pair on the bottom surface to the IC.

    In terms of grounding of the IC, the datasheet mentions the coming together of the analogue ground and power/digital ground at either the PGND pin, near the VCC capacitor PGND pin or near the PGND connection of CS, CSG, etc. pins. In practical terms, can I maintain two solid GND fills on the bottom side of the board, each with vias into the GND plane (layer 2) and top side GND fill, and have the two fills meet at one of these specified points?
  • Hi Jars,

    Please take a look at this blog series covering layout suggestions for the LM5175 (similar to the LM5176). This should help cover a number of your questions.
    e2e.ti.com/.../four-switch-buck-boost-layout-tip-no-1-identifying-the-critical-parts-for-layout


    Regarding the Kelvin connection on the current sense resistor it is best to run them to the middle of the current sense resistor. This will help minimize any offset from the signal.

    Typically there is a AGND polygon that helps to isolate the noise sensitive signals for high currents and ground bounce. This should be connected to the PGND plan on the exposed pad on the back of the IC. Please take a look at the LM5176 EVM for an example of this implementation.

    Thanks,

    Garrett
  • Thanks Garret, your help is much appreciated as always. I read through the linked blog, which was very helpful, and have also reviewed the gerber files for the LM5176EVM as suggested. I'm a little confused with the EVM files however, as the gerber viewing programs I have don't seem to show fills or planes? I.e. I can see IC pads, traces, etc. on the different layers, but where a via is used, or an IC pad is directly on a polygon, I have no visibility.

    Having said all that, I've put what I've learnt into practise with my layout as per the below images. I have managed to shift the power circuitry up by just enough to fit the LM5176 underneath the sense resistor (on the back side of the board). I've also changed the footprint of the current sense resistor, so the Kelvin connections originate from the centre of the pads as you recommended. The majority of the components seem fairly compact, the only exceptions being some of the sense and gate traces going to the MOSFETs; I don't know if this can be helped, nor if it'll cause much of an issue?

    I've used a small polygon (pink) to connect VISNS and the diode/resistor circuit to the input rail (VBATT_FILT) on layer 3, otherwise everything is on the top and bottom layers. In terms of grounds, I've used the same approach (as far as I can tell, given the aforementioned fill/plane via issue) by grounding the analogue pads to the exposed pad under the IC. I've created a ground fill on the bottom layer (green) to connect all the ground pads of the various capacitors and resistors on the upper side of the IC; should I connect this fill to the analogue pad/exposed pad only, or is my use of vias down to the GND plane acceptable?

    Is this general layout looking ok? Is there anything glaringly obvious that I've missed or done wrong? I added some meandering to the current sense traces, as I'm treating them as a differential pair. I'm not sure if this is required or not, but I figured length matching couldn't hurt.

    Image 1: Updated layout with top (red), bottom (green) and layer 3 (pink) traces.fill shown.

    Image 2: Updated layout with top and bottom planes and traces removed to show placement of ICs.

    Thanks!

  • Hi Jars,

    The general layout looks good. If you have followed the blogs and the information in the datasheet then you should be fine.

    Thanks,

    Garrett
  • Thanks Garrett, much appreciated :)