• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Subscribers 64 subscribers
  • Views 696 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCD90320: Anti aliasing filter for voltage monitoring

Sebastian Ciesluk80
Expert 1051 points
Part Number: UCD90320

Hi , This device as well as it's prececessor (UDC90120) do not mention any anti aliasing filter for voltage measurements built inside teh chip or required externally . Monitored voltages will have 5-10 % noise due to switched mode power supplies, what is the rationale behind ommiting this type of filter ?

If it is however implemented what is teh characteristic of this filter ( cut off frequency,  order , phase shift, pass band  ripple)

Regards

Sebastian

  • 0
    TI__Guru 58060 points
    Hello
    There are many factors that can contribute to ADC accuracy
    • Reference voltage inaccuracy due to V33A ripple
    • Noise on MON pin
    • Grounding noise
    • Voltage divider resistor accuracy
    • Incorrect scale ratio in configuration
    • High input impedance to MON pin since there is a leakage current.


    we recommend 100nF decoupling capactitor to filter out nose, there shall be no large current in the ground paths use to measure the voltage.
    Regards
    Yihe
  • 0 in reply to yihe
    Expert 1051 points

    Thank you very much,

    I am asking for anti aliasing filter on ADC input for voltage monitoring , since the monitored voltage can be quite noisy ( as it can be from switch mode psu). I found no references to any cap on these inputs?

    Sebastian

  • 0 in reply to Sebastian Ciesluk80
    Expert 1051 points

    Sorry for nagging , is there anyone able to help ? Trying to get directly to TI FAE but no success so far.

  • 0 in reply to Sebastian Ciesluk80
    TI__Mastermind 24075 points
    Hi Sebastian,

    Sorry for the late reply. The engineer supporting this part is out of office.
    Usually the input filter of ADC has very small RC constant.
    Is it possible to add external 100nF decoupling cap as Yihe suggested?

    Thanks
    Qian
  • 0 in reply to Qian Chen
    Expert 1051 points

    Hello and thanks for update.

    The decoupling can be added but I think it is not related to the aliasing noise from the input of ADC. I guess you talking about sampling capacitor inside teh ADC. Probably he 3dB BW of such a filter is very high so does not filter aliased noise. So how we deal with aliased noise in this device?

    Sebastian

  • 0 in reply to Sebastian Ciesluk80
    TI__Mastermind 24075 points
    HI Sebastian,

    In your first post, you said the Monitored voltages will have 5-10 % noise. This is external noise and can be filtered by external filter such decoupling cap or RC filter.

    Regarding the aliased noise inside device, did you already do some test and notice the measurement error caused by intenla aliased noise?

    Thanks
    Qian
  • 0 in reply to Qian Chen
    Expert 1051 points

    Thanks

    Yes, I see now where the filter should go. Even in very well designed PDN systems we will see noise due to ripple or transient load if we supplying complex SoC or Fpga. Fully agree that we can keep adding filters minimising it but it still be there to certain extent and should alias back when sampled.

    No I have not done any tests on this device , just thinking how well it would perform as voltage and power monitor.

    Sebastian

  • 0 in reply to Sebastian Ciesluk80
    Expert 1051 points
    Just to clarify, stlill trying to get any answer what is the view on aliased noise into the ADC , is there anything in the chip to filter it out, if not what is the rationale of not requesting additional filtering to be added on input to adc like simple 1 pole RC filter ? ( I can add it but it seems TI does not consider this a problem - why?)
  • 0 in reply to Sebastian Ciesluk80
    Guru 140200 points

    Hi Sebatian,

    it is assumed that the supply voltages you intend to monitor are well regulated and free of excessive noise. 10% ripple and noise is way too much for a proper design. Think of the many CMOS-OPAmps which have a maximum supply voltage of 5.5V and are powered with 5V. With 10% ripple and noise you would lose all the safety margin and there would not be any headroom for the supply voltage tolerance. A usual 5V supply can have 5% tolerance. So, ripple and noise should be well under 5%.

    Also, this application is no analog signal chain, where you are interested in the frequency domain and where you have out of signal band noise you want to reject and prevent from being folded back into the signal band. Here the time domain is relevant. You take a sample at a certain moment and that's it. The ADC conversion rate on each ADC channel is 1MSPS. This is fast enough to prevent any additional error. So, there's no need for a sophisticated anti-aliasing filter. Add the recommended 100nF cap, if your supply is noisy. But that's it.

    Kai

  • 0 in reply to kai klaas69
    Expert 1051 points
    Hi,
    Thanks for that , could not agree more , this is also my view , I believe that noise around the sampling frequency is so small that aliassed artifact will noyt affect greatey the measure signals. Sorry for pressing on this comment but wanted independent confirmation that I am correct.