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[FAQ] TPS2373: What is the functionality of the TPH, TPL, and /BT pins for TIs IEEE802.3bt-ready PoE PDs?

Part Number: TPS2373

What is the functionality of the TPH, TPL, and /BT pins for TIs IEEE802.3bt-ready PoE PDs? 

  • The TPH and TPL pins are used to communicate within the PD system the maximum power allocated to the PD. This is communicated from the PSE to the PD by the number of class cycles that the PSE sends/the PD receives. 

    Let's go through a few examples to gain a deeper understanding:

    1.      When the PD receives one class cycle from the PSE, TPH = HIGH and TPL = HIGH. This indicates that the allocated power at the PD is 12.95W max via 2 twisted pairs.

    2.      When the PD receives two class cycles from the PSE, TPH = HIGH and TPL = LOW. This indicates that the allocated power at the PD is 25.5W max via 2 twisted pairs.

    3.      When the PD receives three class cycles from the PSE, TPH = HIGH and TPL = LOW. This indicates that the allocated power at the PD is 25.5W max via 4 twisted pairs.

    4.      When the PD receives four class cycles from the PSE, TPH = LOW and TPL = HIGH. This indicates that the allocated power at the PD is 51W max via 4 twisted pairs.

    5.      When the PD receives five class cycles from the PSE, TPH = LOW and TPL = LOW. This indicates that the allocated power at the PD is 71W max via 4 twisted pairs.

    This information and more can be found in the Table 2 of the TPS2373 datasheet as shown below:

    The /BT pin is used to "inform" the PD that the PSE will support the new IEEE802.3bt MPS timing requirements. That is, if the PD sees a long 1st class finger as shown below, this indicates that the PSE can support the new .bt MPS timing. Under this condition /BT = LOW. 

     

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