Part Number: LMR23630-Q1
We are using the LMR23630-Q1 to step down 12V to 3,8 for a GSM/LTE modem. The WeBench design recommends a 200 uF cap with ESR less than 30 mOhms at the output pin of the DC/DC convertor. The reference design for the GSM modem recommends two 100 uF bypass capacitors at the VCC pins of the chip.
What should I be wary of here? The trace from the LMR23630 to the modem would be around 5 inches long.
1) Should the bypass capacitors at the modems VCC also be low ESR?
2) Should I also consider the bypass capacitors at the modem in determing the stability of the output of the DC/DC. Should I stay below the upper bound mentioned in the WeBench design?
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In reply to Timothy Hegarty:
Thank you for the comprehensive answer! That helps a lot.
I have a related question that I hope you could help me with.
Our power stage includes two LMR23630s, one stepping down to 3,3V and the other to 3,8V.
To reduce the conducted emissions I have added the following LC filter at the input to the convertors.
I have an additional 5V LDO stepping down from 12V where I need to add a high ESR aluminium electrolytic cap to smoothen out the input transients.
Show in the below schematic are the nets 12V and 12V_DCDC.
Is it the correct decision to connect the LDO input to the '12V' net and not the 12V_DCDC net, before (or after if considered from the point of the DC/DC) the LC filter?
Or will this high ESR bulk cap have an effect on the LC filter?
In reply to Pradeep Mohan:
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