Hello Team
When switch from RT mode to CLK mode, after about 10us, the PG pin will drop. Is it correct?
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Hi Xiao,
I took the LMZ30606EVM with the following application: Vin = 5V, Vout = 3.3V, Fsw_default = 1MHz, Fsw_clk = 2MHz. Attached is a scopeshot of the bench test. The test sequence is as follows: power up with Fsw_default (RT mode) -> switch ON Fsw_clk (CLK mode) -> switch OFF Fsw_clk (back to RT mode).
Here you will notice that when transitioning from RT mode to CLK mode there is no drop in PWRGD. However when you transition from CLK mode back to RT mode there is a temporary drop in PWRGD. Note that the datasheet details to not switch from CLK back to RT mode(Section 8.12).
Regards,
Jimmy
Hi Xiao,
I'd like to further enforce that the datasheet specifically does not recommend to switch from CLK mode back to RT mode because of internal switching frequency drops to a lower frequency before returning to a switching frequency set by the RT resistor. If the output voltage droops too much during this CLK mode to RT mode transition, the PWRGD pin temporarily going LOW. This can be seen in the waveform I sent you where Vout slightly droops down.
Because of this, I believe this drop is an artifact caused by this invalid transition. This suggests that the part should not be used in dynamic switching frequency applications.
Regards,
Jimmy
Hi Xiao,
If possible can you also attach your schematic. I want to have a full picture of your system. What RT resistor were you using? Ideally I want to test the EVM with your system application to get an apples to apples comparison.
Just to clarify, it sounds like you are observing the PWRGD going low after transition from RT mode (set by RT resistor) to CLK mode (external clock generated). As I've shown you above in the scopeshot, I didn't see any unexpected PWRGD drop.
Regards,
Jimmy