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BQ34Z100-G1: Sleep Mode Acquisition Timing

noel lanier
Prodigy 100 points
Part Number: BQ34Z100-G1

My application may see currents in excess of 150A.  A current sense resistor is just not practical.  I intend to use an Allegro hall effect device and scale the output to the SRN input range; SRP tied to stack '-'.  The current consumption of this device (15mA max) is not insignificant.  While the BQ34Z100-G1 is in sleep mode I will power down the Allegro device to optimize battery consumption.  The standard 'Alert'  options (7.3.14 Table22, DS July2016) do not offer an "awake" output.  The last sentence of the paragraph under Table21

"See the reference schematic (Figure 17) for filter implementation details if host alert sensing requires a continuous signal."

implies that pin TS/P6 should be used for this function.  ("Host Alert" not to be confused with "Alert".)  Monitoring pin11 on my EVM, while the 'G1' is in sleep mode (no I2C activity), I see a 140ms width pulse every 20s.  This is consistent with biasing the external thermistor prior to reading.  I intend to use this signal to gate power and enable biasing of the Allegro device.  The 'G1' datasheet does not give any timing information relative to this signal and internal operations.  The 'G1' datasheet does mention a 1s "typical" acquisition time (6.10, 'tSR_CONV').  This appears to be four times longer than expected for the same bit resolution relative to (6.11, 'tADC_CONV').

What is timing relationship of the TS/P6 activity to V(SRN) and V(SRP) conversion?

When are the inputs sampled? 

Do the inputs need to be stable for the entire conversion period?

Thank you,

Noel Lanier

  • 0
    TI__Mastermind 42535 points
    Your question will be answered in 1 week or less.
  • 0 in reply to Batt
    TI__Mastermind 24870 points
    Hello Neol,

    Actually, before providing answers, I would like to understand the application, is it sustained 150 A?

    Even peak currents would be too hard. The coulomb counter is a continuously integrating CC. We dont' sample the current so we should integrate the long term average.

    However, for your end application, the device may not be suitable. Can you tell me more about the application? What's the cell stack voltage?
  • 0 in reply to Kang Kang
    Prodigy 100 points

    Hello Kang,

    The pack is 14S1P LiPo.  The stack voltage is (4.2 x 14) or 58.8V  This is below the specified scaled maximum of 65V for the 'G1'.

    Typical current draw will be (40 to 60)A.  Current may peak at 80A.  In a bussed (or shared) arrangement current draw would be roughly twice that but relaxed a little so 150A peak.  However, this is beyond the maximum specified sustained current for the cells.  This would only be momentary.  Also, this would only occur in a fault situation where one battery pack has failed and an adjacent pack must handle both loads to prevent destruction and loss.

    I am aware that the coulomb counter is constantly integrating.  The gated active current sense circuit would introduce an error.  The integrated value would make it appears as though the sense circuit current is constant and not gated for a short interval.  My solution is to leave the active current sense off during some awake periods.  This should read as zero.  Given sufficient number of awake periods the integrated value should be close enough to the actual value that the error is less then the precision of the counter.  A micro would track the real current and determine when to enable or disable the sense circuit to compensate for the induced error.  The micro may also be used (if needed) to wake up before and anticipate when the G1 will wake-up so that it can enable the sense circuits prior to G1 measurement.

    At 15-bits half-range:  150A/16384 = 9.2mA/lsb which makes 15mA barely measurable and probably lost in the noise.

    At 14-bits half-range: 150A/8192 = 18.3mA/lsb which makes 15mA below this limit.

    So is this exercise completely moot.  The gated sense circuit will still help optimize battery usage.

    Thanks,

    -Noel Lanier

  • 0 in reply to noel lanier
    TI__Mastermind 25955 points
    Hi Noel,

    For timing information, please hook the device up to a source meter and allow the device to go to sleep (where Ts pulses are seen every 20s). Prior to the TS pin going high, the ADC will energize and more power will be consumed. Calculate the delta from this instant of time until the rising edge of the next TS pulse for use as an offset in normal mode.

    Sincerely,
    Bryan Kahler
  • 0 in reply to Bryan Kahler
    Prodigy 100 points
    Hi Bryan,

    I will do this on my EVM. Are you suggesting that the timing will be variable enough part-to-part that I will need to do this in normal operation Or is this timing just not characterized?

    Since this occurs prior to the assertion of TS does this mean SRN, SRP sampling also occurs prior to that event?

    "offset in normal mode" do you mean offset in 'sleep mode'?

    Since this a firmware based device should I assume that this offset will need to be re-characterized if/when there is a firmware change/update?

    Any chance of getting a firmware register+bit option to enable TS early as soon as the G1 comes out of sleep?

    Thanks,
    Noel Lanier
  • 0 in reply to noel lanier
    TI__Mastermind 25955 points
    Hi Noel,

    Could you please private message me to further discuss the application and volumes?

    Sincerely,
    Bryan Kahler