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Part Number: UCC27712
Hai i am designing a 1.65kw solar inverter.i have h-bridge in the output side for 50 Hz ac generation.i am using IGBT STGW20NC60VD AND ARE DRIVEN BY UCC27712DR for ac generation.I have applied spwm with 90 percent duty cycle in the high side and simply square pulses on the low side for ac generation.I found the ringing and peaks as shown in the image in the gate signal which are causing the mosfets to be too hot when high loads are applied at the end of the h-bridge.What could be the possible reason behind this issue?
The image shows signals ,when the gates of the IGBT were probed.
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In reply to Don Dapkus:
In reply to Amal:
In reply to Richard Herring:
sorry for late Response,we were having holidays till yesterday.
The switching frequency of half Bridge is 5KHz.Yaa its true that the VDD caps is not 10x the bootstrap.Should i decrease the bootstrap cap and increase the VDD caps.Or Should i change them?
The following are the HS AND HO SIGNALS probed with respect to ground.
Zoomed image of HS AND HO are also attached.Please see the Image of Ho probed with respect to ground.I have also attached the Input waveform to the gate driver driving a half cycle.
Please note that SPWM is given to high side and square pulses to low side fets.
i have also attached the routing scheme implemented on my board.please comment on same.
Thank you for the details on the operation, scope plots and layout.
First I want to review the bootstrap capacitor and VDD capacitor values based on the operating frequency and IGBT part number. The value selection guidelines can be found in the datasheet section 8.2. http://www.ti.com/lit/ds/symlink/ucc27712.pdf
First determine Q total based on device Qg and HB Iq. Since there is a 5.1K Ohm gate to source resistor I will add this current to the Iq. Current from 5.1k resistor: Vdd-Vf/Rgs, 11.3V/5.1kOhm= 2.2mA. This value of Rgs and low frequency will discharge the HB cap noticeably and require larger value.
Qtotal=Qg +( Iqbs+IRgs)/Fsw, Qtotal= 100nC + (2.2mA + 65uA)/5kHz=553nC. You can see the Rgs current dominates the required charge since the device is 100nC Qg.
I would suggest having the Cboot at 1uF to 2.2uF, maybe change the R33 to 10 k Ohms for more margin.
With Cboot at 1 to 2.2uF, the existing Vdd capacitance of ~24.7uF meets the recommendation of CVDD being 10x the Cboot value.
On the scope plots second to bottom zoomed in . The CH1 high pulse appears to be ~10V higher than the channel 3 switch node. The remaining waveform appears to be the same which ideally HO will be the same as HS for 0V differential. The very last plot it is not clear of this condition, or trace signals can you explain the last trace signals, and if this is expected operation?
On the layout plots: Most component placement and trace length looks good. I have a couple of comments. The trace to the LI input looks very close to LO output and HS/HO output. There may be some noise coupling from the high voltage and dV/dt traces to the LI input. Move HI and LI traces as far away from driver outputs as possible. It is not clear where the driver ground reference path to the low side power device emitter connection is routed. Make sure the driver current path length to the gate and from the emitter back to driver ground is not long.
Since you are driving IGBT, have you tested using higher drive voltage such as 15V to see if this improves the operation?
If you have more questions or concerns please reply to this post. If we resolved the concerns please confirm on the thread.
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