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UCC21520: Excess current consumption during start up

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Replies: 5

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Part Number: UCC21520

HI,

I am using UCC21520 for driving Half bridge LLC converter(Switching frequency:700KHz to 1MHz).

In actual condition,the top FET drive disabled due to gate driver UVLO.Then the supply for floating LDO is given through external floating supply(TDK lambda ).

During start up,the gate driver is driving more current(3A) from the floating supply of Top FET for a period of 500us .

1.Why that much current is drawn during start up?

2.During start up,The gate control is also distorted.This distortion is making the converter operation in capacitive region.

The above abnormalities are found only for TOP FET drive and there is no distortion in Bottom gate drive and excess current.

With regards,UCC21520 driver schematics.pdf

P.Selvam

  • Hi P. Selvam,

    Sorry you are having issues with your design. My colleague will investigate on Monday.

    Best regards,

    Don Dapkus

    Gate Driver Applications

    Dallas, TX USA

     

    We have an excellent training series that can help answer all your questions about our gate drivers. It is indexed so you can jump right to the section you want! You can find it here. A second series focused 100% on Isolated Gate drivers may be found here.

    We also provide models for our gate drivers to accelerate your time to market. You can find them in the Product Folders under the "Design and development" tab:

  • In reply to Don Dapkus:

    Issue 2:
    In the same circuit,If the FET fails and gives impedance of 10 ohm between gate and source.If it happens,What will happen to the gate driver?
    In above condition,the gate driver also failed along with bootstrap LDO(TPS7A1601) and bootstrap diode.
  • In reply to Selvam Perumal:

    Hi Selvam,

    Are you using UCC21520A? Please note that UCC21520A has a UVLO turn-on threshold on VDDA/VDDB of up to 6.3V max. It looks like the supply has been adjusted to nominal 6.5V, but if there is too much inductance in the supply loop, the UVLO threshold could be unexpectedly tripped on startup when switching at very high frequency. Minimize the distance between the LDO output and the UCC21520A bypass capacitor.

    There are several robustness concerns with the input to the circuit:

    • The INA/INB connections do not have the low-pass filter capacitors suggested in the datasheet. These capacitors are critical for ensuring INA/INB remain stable during high dv/dt events such as LLC startup. Small values between 10pF and 47pF should be sufficient. For optimal performance, ensure that the capacitors are grounded directly to a low-impedance ground path, such as an unbroken plane beneath control-side circuitry.
    • If the DISABLE pin is unused, it should be directly shorted to GND. By connecting to GND through a 4.7kΩ resistor with no active net driver, high dv/dt can capacitively couple currents onto the DISABLE pin high impedance and cause false disable triggering.
    • The DT pin should be tied to VCCI (if unused) or a 2.2nF capacitor to GND should be added to the DT pin (even if no DT resistor is used) for added noise immunity. Like with the other input pins, high dv/dt can capacitively couple noise onto the DT pin, causing distortion in the programmed dead time. This is especially critical at high drive frequencies (>500kHz) since DT distortion represents a significant fraction of the total duty cycle at these frequencies. The noise is mitigated with the addition of a 2.2nF capacitor to GND, or if DT is unused by tying DT to VCCI.

    The waveform in the linked schematics shows heavy distortion on the INA input. This is often a result of not using the suggested capacitors on the INA/INB connections, and I recommend using them whenever possible. This could also be a result of a long measurement loop, so please make sure that the loop area is minimized with short connections while probing the input.

    If the FET fails with a low impedance short between gate-source, the driver will likely be damaged because it will draw very high current during the ON portion of the duty cycle. This also helps to explain why the bootstrap LDO and diode could fail, since there would be substantial current draw on the failed output.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Thank you for your response.
    In Out pins of gate driver,I can see ESD diodes between OUT B and VSS B.
    During fall time of output,I am observing negative spike upto -3V for a time period of 20ns.
    As stated in Absolute maximum,the out pin voltage should be between -0.3V and VDD-VSS.
    Do I need to clamp the negative spike by using external diode across OUT and VSS ?
    If I didn't place the external clamping diode,Will the negative spike damage the gate driver?
  • In reply to Selvam Perumal:

    Hi Selvam,

    The absolute maximum ratings include a repetitive transient rating for OUTx to VSSx of -2V for 200ns. If you see voltage spikes which exceed this direction, a schottky clamp between OUTx and VSSx can reduce the spiking to within the maximum ratings.

    The OUTx pin relies primarily on the body diodes of the internal low-side output MOSFET during negative spikes. Consequently, predicting the point of failure due to negative spiking is inexact at best, and there is a strong interdependency between the die temperature, spike magnitude, and spike duration. -2V for 200ns is TI's suggestion for the negative spiking limit, but if driver power dissipation and die temperature are minimized, operation with larger spikes (such as the -3V for 20ns seen in your application) can be possible. I recommend operating within the limits suggested in the absolute maximum ratings whenever possible.

    Regards,

    Derek Payne

    Texas Instruments

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