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UCC21520: Reason for UCC21520A Device failure showing Impedance between INB and GND,VCCI and GND as 52 ohms
Part Number: UCC21520
I am using UCC21520 for driving Half bridge LLC converter(Switching frequency:700KHz to 1MHz).
In actual condition,the top FET drive disabled due to gate driver UVLO.Then the supply for floating LDO is given through external floating supply(TDK lambda ).
During start up,the gate driver is driving more current(3A) from the floating supply of Top FET for a period of 500us .
1.Why that much current is drawn during start up?
2.During start up,The gate control is also distorted.This distortion is making the converter operation in capacitive region.
The above abnormalities are found only for TOP FET drive and there is no distortion in Bottom gate drive and excess current.
With regards,UCC21520 driver schematics.pdf
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In reply to Don Dapkus:
In reply to Selvam Perumal:
Are you using UCC21520A? Please note that UCC21520A has a UVLO turn-on threshold on VDDA/VDDB of up to 6.3V max. It looks like the supply has been adjusted to nominal 6.5V, but if there is too much inductance in the supply loop, the UVLO threshold could be unexpectedly tripped on startup when switching at very high frequency. Minimize the distance between the LDO output and the UCC21520A bypass capacitor.
There are several robustness concerns with the input to the circuit:
The waveform in the linked schematics shows heavy distortion on the INA input. This is often a result of not using the suggested capacitors on the INA/INB connections, and I recommend using them whenever possible. This could also be a result of a long measurement loop, so please make sure that the loop area is minimized with short connections while probing the input.
If the FET fails with a low impedance short between gate-source, the driver will likely be damaged because it will draw very high current during the ON portion of the duty cycle. This also helps to explain why the bootstrap LDO and diode could fail, since there would be substantial current draw on the failed output.
In reply to Derek Payne:
The absolute maximum ratings include a repetitive transient rating for OUTx to VSSx of -2V for 200ns. If you see voltage spikes which exceed this direction, a schottky clamp between OUTx and VSSx can reduce the spiking to within the maximum ratings.
The OUTx pin relies primarily on the body diodes of the internal low-side output MOSFET during negative spikes. Consequently, predicting the point of failure due to negative spiking is inexact at best, and there is a strong interdependency between the die temperature, spike magnitude, and spike duration. -2V for 200ns is TI's suggestion for the negative spiking limit, but if driver power dissipation and die temperature are minimized, operation with larger spikes (such as the -3V for 20ns seen in your application) can be possible. I recommend operating within the limits suggested in the absolute maximum ratings whenever possible.
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