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UCC28251: UCC28251 start-up SR timings

Part Number: UCC28251
Other Parts Discussed in Thread: UCC28250

Hello.

I'm designing a power supply that need pre-biased start-up functions for parallel operations. PWM controller is UCC28251 placed on the primary side.

SR outputs are overlapping signals at normal conditions, but during soft-start interval they starting with no overlapping (less than 50% duty cycle) with dead-time equal to PS delay.

Is it OK for this controller? Can this issue cause some troubles including power supply damaging during pre-biased start-up?

Thanks for Your answer.

  • Hi Max,

    I have contacted one of my colleagues to answer this question.

    Regards,
    Teng
  • Hello Max,

    Regarding for the Pre-bias implementation, UCC28251 is same as UCC28250 so you can use the application paper under below link as a reference.

    www.ti.com/.../slaa477.pdf

    Best Regards

    Frank

  • Hello, Frank.

    Of course, Pre-Bias start-up implementation is the same as UCC28250 like in slaa477.
    Datasheet for UCC28251 says signals SRA and SRB have a minimum 50% duty cycle during startup. But unlike datasheet they start with duty cycle LESS than 50% with NO overlapping. This issue can be critical for pre-biased start-up.

    Best Regards,
    Max.
  • Hello Max,

    Are you considering  it a issue that the minimum duty cycle is a little smaller than 50%? Could you post a waveform that shows how issue happens in your system or an explanation why you think it is a issue?

    Best Regards

     Frank

  • Hello Frank

    Here is scope explaining our problem.

    Upper two traces are OUTA & OUTB signals, lower traces are SR outputs directly from the IC. Clearly we can see non-overlapping SR signals with duty cycle less than 50% at start-up. For pre-biased start-up the path for output inductor reverse current (from output to input side) should be provided. But this path is broken during SR dead-time.

    Best regards

    Max

  • Hi Max,
    Thank you for capturing the waveforms, now I understood your questions. I agree that negative current could cause the voltage over-stress on drain to source of SR during SR dead time, but, without the overlap of SR drive signals, where the negative current comes from? Without negative current, I do not expect the over stress on drain to source of SR.

    Best Regards
    Frank
  • Hi Frank


    Power stage can act as current-fed topology due to SRs on the output side, transferring energy from the output to the input can be possible. In that fact, we should care about SR's soft-start for pre-biased output.
    Also like for current-fed topologies we should care about inductors energy path when power stage transfers energy from the output to the input. Otherwise inductive spikes can cause voltage over-stress and also damage MOSFETs.

    Output inductor backward current can be obtained during start-up with pre-biased output - inductor starts to raise energy from pre-biased output voltage (this one can be clearly observed for current-doubler rectifier, SR shorts inductor directly to the output) then this energy should be transferred.

    We simulated this start-up with and without overlapping SR signals, backward current from the pre-biased output to the input was observed for both cases. Anyway since we can't transfer all stored energy through the transformer we should use various voltage clamping circuits to prevent over-voltage stress, but more energy needs to be clamped when SR signals are non-overlapping.


    Best Regards
    Max
  • Hi Max,

    Without the cross-conduction of SR, the switching node of output choke is equal to Vin/N if current negatively flow and feedback to input, where N is transformer’s turn’s ratio from Primary to secondary. In regulation system, Vin/N should be higher than Vout. Therefore, the positive voltage-second avoid negative current from happening. But if the Vin/N is smaller than Vout, the negative current will certainly happen but it is not a real case for regulation power system, which is not the targeted application of UCC28250/1 who is controller for regulation system.

    If the answer above is not consistent with your simulation, could you explain how your simulation setup and at what time the negative voltage-second across output choke and negative current via output choke appears?

    Best Regards
    Frank