Hi,
Is it correct that WDO signal is not kept at low when fault occurs? (Now is high low switching)
Schematic is as below.
Thank you.
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Hi,
Is it correct that WDO signal is not kept at low when fault occurs? (Now is high low switching)
Schematic is as below.
Thank you.
Cindy,
Do you have scope captures of your RESET and SENSE during this time?
Thanks,
Abhinav.
Cindy,
I'm still a bit confused: do you mean that you're expecting WDO to go high after the fault again?
Thanks,
Abhinav.
Hi Abhinav.
No. Datasheet shows that WDO will be set to low after fault stop, but our waveform is kept at high after that.
We want to know whether this is correct or not.
Thank you.
Best Regards,
Cindy
Cindy, Andrew,
WDO is in a high impedance state after tRST, and since this is being pulled up to Vdd, this should hold a default high state. This should be correct.
Thanks,
Abhinav.
Andrew,
It appears that the schematic shows SET0 = logic high, SET1 = logic high, CWD is pulled high with resistor, and CRST is pulled high with resistor. This means the upper boundary timeout is 11ms and the reset delay, tRST is 10ms. This is shown correctly in the scope capture. I don't see any issue. Please correct me if anything is misunderstood. Thanks!