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CSD19536KTT: SOA

Shota Mago
Expert 6580 points
Part Number: CSD19536KTT
Other Parts Discussed in Thread: LM5121,

Hi team,

My customer use CSD19536KTT for inrush current limit circuit of LM5121.

Could you check if below condition and attached waveform is within SOA?

  1. Id：14A／10ms
  2. Id：8A／20ms

I look forward to hearing back from you.MOSFET_Vds Id.pdf

Best regards,

Shota Mago

  • 0
    TI__Mastermind 29525 points

    Hi Mago-san,

    I reviewed the waveform and SOA curves. At VDS = 31V, the 10ms SOA current is about 10.5A. Therefore, 31V/14A/10ms violates the SOA limit. We don't test at 20ms (only 10ms and 100ms). At VDS = 31V, the 100ms SOA current is 5.4A. Based on this and the 10ms limit, I think 8A is border line. We do test to failure and derate SOA from the failure point so we can guarantee operation up to the SOA limit defined in the datasheet plots. However, I would not recommend operating the FET under either of these conditions.

  • 0 in reply to John Wallace1
    TI__Expert 6580 points

    Hi John-san

    Thank you for your quick reply and kind explanation.

    Let me check one thing.

    In accordance with customer's waveform, Vds decreases while Id is constant.

    Should we assume constant Vds/Id with worst condition when applying to SOA grapgh? 

    Or is there other calculation to judge SOA when Vds is not constant?

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Mastermind 29525 points

    Hi Mago-san,

    I will check with a colleague. How long does it take for Vds to decay from 31V to 0V?

  • 0 in reply to John Wallace1
    TI__Expert 6580 points

    Hi John-san

    Please assume (1)9ms and (2)18ms from 31V to 0V decrease in the waveform.

    Thanks for your kind cooperation.

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Mastermind 29525 points

    Hi Mago-san,

    I apologize for the late response. I submitted a response on Friday but it does not look like it went thru correctly. I will repeat it here again.

    I discussed this with a colleague. Because the SOA curve is not linear, we don’t think its 100% accurate to average the VDS and say that 31V for 10ms ramping down is the same as 15.5V for 10ms exactly. The higher the voltage, the less energy the part can sustain. So as a worst-case scenario, we generally assume constant VDS.

    We think the actual capability of a pulse that looks like the one in the diagram you provided (as opposed to a square wave) is a lot closer to the 15.5VDS, 10ms line on the SOA than the 31VDS, 10ms capability. If we average the voltage at 15.5VDS then the 10ms SOA current is much higher at about 33A. However, we would definitely want to have enough margin to feel comfortable with this assumption. Let's use 50% such that VDS = 15.5 x 1.5 = 23.25V and round up to 24V. At VDS = 24V, the 10ms SOA current is 15.7A.

    If I use the same logic for the 20ms application but use the 100ms SOA line, the 100ms SOA current at VDS = 24V is 8A.

    Unfortunately, we don’t have any data to back that up – we have only ever tested square waves, not triangle waves.

    Is there anything the customer can do from a design perspective with the LM5121 to reduce the stress on the disconnect/inrush FET?