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# LM5121-Q1: Iripple and Vripple of the output capacitor COUT

Part Number: LM5121-Q1

Hi,

When we make the detailed design procedure of LM5121, we don't understand the equation (30) and (31) in 8.2.2 Detailed Design Procedure.

Could you please what is Iripple_max(cout)? And why Iripple_max(cout)and Vripple_max(cout) are calculated like those two equation?

Thanks&Best Regards,

Wenxiu

• Hi Wenxiu,

Thank you for posting.  This needs to refer to a power electronics text book to get a good understanding. These are fundamental equations. Let me try my best to explain here.

The boost duty cycle is  D= (Vo-Vin)/Vo.  So when the sync FET conducts, it is 1-D = Vin/Vo.

The output current Io, which must be supplied by the sync FET during 1-D.  So the sync FET current pulse's average top is Io/(1-D).   The estimated ripple current, assuming half of the pulse current goes into the capacitor and the other half goes to the load, will be equation (30).

The ripple voltage consists of contributions from ESR and from the pure capacitor. The ESR part is the pk current x ESR directly.  The number 4 in the second term comes from the calculation for total charge each cycle exchanged with the Cout.

Thanks,

Youhao Xi, Applications Engineering