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UCC2897A: Design is sometimes shutting down leaving the control circuit consuming a lot of power.

Part Number: UCC2897A

Hi!

We are using the UCC2897A in a design converting  90V-250V to 24V (70W).

So we use a series regulator to lower the VIN-voltage to approximately 20V to deal with the 110V limit on VIN. Our bias winding is week at low loads so we need to supply the VDD via zener in light load situations. This works fine and so does the rest of the converter but sometimes, after running several days, can the converter die. I still haven't figured out what happens but it is difficult to start it again. Wait a while and then it starts as normal. This happens on several converters.

I can't measure on the converters since they are in system tests but I have triggered the fault once in our lab.
After this I have provoked the converter wit heat and re-starts and sometimes the converter will not start. In this case has the control circuit normal voltage on VIN and VDD but the control circuit appears to be dead or sleeping, VREF = 0V etc. The series regulator becomes hot and the input current is 15mA-20mA which almost all is passed trough the UCC2897A, but it is not over heating as far as I can see with IR-camera. The cooling via the thermal pad prevents this. Or is it internally? 

I have checked the start conditions p.18 and it looks okay.

The output has a large capacitor for hold up so the output is remaining high (not zero) when the input is cycled. This seems to work in our tests but there is no pre-bias information in the data sheet. Maybe we have missed something regarding this.

Any ideas what to search for in my investigations?

Best Regards / Daniel

  • Hello Daniel,

    It is significant  that VREF= 0V during this situation. This will disable the ic and discharge the soft start pin.
    You mention that your bias supply has some issue and you are biasing VDD externally.
    Since VDD is used to generate VREF
    I would review this circuit and ensure that VDD is a minimum of 8.5V in all operating conditions.
    Check the capacitance on VDD and VREF
    The capacitance on VREF and VDD should be in a minimum ratio of 1:10.

    Regards

    John

  • Hi! Thanks for the quick answer. I will check this again, done it before without finding any problems with the level.

    Our problem is that the VDD level drops from 12V to minimum 9V when the load is small. This should be okay but maybe noise is to high? We have 1uF ceramic and electrolytic 100uF on VDD right now. Should be sufficient for our application?

    Best Regards / Daniel

        

  • Recreated the problem when starting the circuit.

    I had 20V @ VIN and 12V @ VDD but VREF is still zero.

    What could force the reference to zero more then overload (>8mA). We have 4.7k//10nF between VREF and FB. VREF has 1uF ceramic decoupling. 

    / Daniel

  • Hi!

    Any update on this matter? That would much appreciated since I'm running out of ideas what to try.

    Best Regards / Daniel

  • Hi Danie,

    Do you have additional circuitry on the VREF pin ?

    If VDD is within limits and VREF is not in specification itc could be that VREF is overloaded or there is some pin to pin short on the pcb.

    Do you think this is possible?

    Regards

    John

  • Hello again! I've been away and but also done some measurements.

    VREF has the standard  connection to FB va 4.7k for regulation. The feed back signal is noisy so we have 10nF parallel to this resistor to filter out added noise. REF is not shorten, the board works in most cases... :-)

    Unfortunately,  I had to leave the suspicious board away but I'm continuing on a other example. It behaves better but in a similar way. 

    Right now we have C_REF = 220nF, C_DD = 1uF + 100uF and C_SS = 15nF. The feeding of VDD pin has also altered so it is higher in general (added turns to the transformer) and is limited to 15V by a zener diode. So everything is much better now but I still see some phenomenon which I can't understand.

    I found out that the charging of the VDD is dependent on temperature. And the ramp is not constant, so the charge current appears to change depending on on temperature and VDD voltage. See attached figure. In the figure is just the temperature change seen, VIN is connected to an external supply at approximately 24V. 

    Higher temp. ==> slower charging ==> sometimes is the final voltage below 12.7V leaving the controller in a non starting state.
    Should't the J-FET just fill up the VDD capacitors with as long as the VIN voltage is sufficient?

     

    VDD reaches 12.7V and starts charging SS etc. VDD falls and then start conditions are fulfilled. It starts switching and VDD rises to 15V.

    Another phenomenon is that the VDD falls due to the weak supply in a no load condition, but it takes 2.5sec after start. Any clues what causes this time constant? I expected this to happen right after the start procedure.    

    Best Regards / Daniel

  • Hi Daniel,

    I notice that the data sheet specifies a typical and maximum value of startup current over temperature but it does not specify a minimum value.

    I can check with QA and see if they have any data for the variation in I_STARTUP.

    Do you know what temperature the device was running at when you observed this effect ?

    Regards

    John

  • Hi!

    We were using a heat gun on quite some distance, temperature monitored with the fingers in the vicinity of the control circuit. So best guess is in the region of 60°C.

    BUT to my embarrassment did I find more consumers on VDD, or rather our AUX_SUPPLY, which probably sinks the voltage by its current consumption. (Too many pages in the schematic apparently... :-)) When these consumers were removed did the design start as intended , even in the conditions where we had problems before. 

    We are still testing if this is the root cause to the behavior in our design and it looks promising.

    Best Regards / Daniel

  • Hi Daniel,

    I will close this post since there has been no new info in last 2 weeks.

    Please open a new thread if you require any assitance

    Regards

    John