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LM5022: UVLO input leakage spec and voltage clamping

Intellectual 1420 points

Replies: 3

Views: 59

Part Number: LM5022


The LM5022 datasheet specifies the abs max voltage level at the UVLO input as 7V.

There is no max value specified.

In the customer's application the input working voltage is 10.5V to 60V.

To ensure this functionality, a 105K + 14k7 UVLO voltage divider was chosen.
At 60Vin the UVLO voltage calculates to 7.37V nominal, potentially higher with 1% tolerance resistors.

I would expect that at that voltage level the hysteresis current generator is no longer functional (saturated).
However, the DC probing of the UVLO pin reads 6.25V which i cannot explain.

1. what is the UVLO maximum allowable voltage?
2. what is the UVLO input current leakage?
3. does the UVLO input have clamping diodes to the comparator's internal bias?
4. if clamping is present, what is allowable current into the diode?
5.if no clamping occurs, is external clamping circuitry needed and what woud be recommended as a low cost solution - a DZ has significant leakage over temp itself, a 431 clamp adds cost and parts count.

there is no app note in the datasheet for this in-spec use case

Thank you.

  • Hi Cosmin,

    Thanks for reaching out with your questions and for using the LM5022.

    The maximum voltage rating of the UVLO pin is 7V. If the voltage is higher than this the pin can be damaged and it is not recommended to us the internal ESD structure to clamp the voltage. And external zener diode should be used. The other option is to change the resistor values to the pin doesn't go above 7V

    What is the input voltage when the UVLO pin is being measured?



  • In reply to Garrett Roecker:

    Hi Garrett,

    With a 105k/15k resistor divider, the reading at the pin is 6.24V at Vin=60V, far from the expected 7.5V - hence the question for the input voltage clamping.

    The needed 10.5V UVLO threshold drives the divider ratio; changing the resistor values will need to keep the same ratio to comply with the spec and not addressing the issue, although higher values would ease the unspecified input clamping diodes stress.

    Using a DZ for clamping is a UVLO tolerance nightmare due to the diode temperature dependent leakage (-40C...+85C testing)

    Thank you

  • In reply to Cosmin P:


    Please contact me directly and we can discuss this issue.