Part Number: TPS54160
I'm testing TPS54160, as you can see the image below, this is the Vsw waveform, and in the red circle is the voltage spike. i'm wondering what caused the voltage spike when mosfet switching?
I think current change so quickly at the switching moment, due to U=L*di/dt, U(voltage) will have a spike. am i correct?
if you have any suggestions, feel free to tell me.
We will reply you in Monday
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In reply to Neal Zhang:
Yes you are correct.
The SW overshoot and undershoot is caused by the parasitic inductance.
Please see the article below for details:
Thanks a lot for you answer, i have several more questions, hope you can help me.
As mentioned in the article:
"The reverse recovery effect of the diode and the slewing of the FET capacitor voltages resultin overshoot of the Control FET current. This current overshoot is absorbed by the output capacitance of the FETs, resulting in overshoot of the Switch Node voltage."
What does slewing of the FET capacitor voltages mean in this article?
And, does output capacitance of the FETs means Co in the circuit below?
In reply to Mason Liu:
When the gate voltage of HS MOS turns it on, it will have slew rate. because the diode has reverse recovery, so the L*di/dt will result in overshoot.
output capacitance of the FETs is the parasitic cap of the FET, not Co.
Please send email if you have further question. firstname.lastname@example.org
Thanks a lot for answering me!
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