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TPS65094: ATX power platform

Hank Chang2
Prodigy 90 points
Part Number: TPS65094

Hi,

      I use the TPS650942 & ATX POWER to design the core power of INTEL Apollo Lake.In the state of S4/S5,the output of Buck1/Buck4/Buck5 is unstable.Why is this?

      Another question is, is VSYS earlier than V5ANA? If not, what will happen?

Thanks

Hank 

  • 0
    TI__Genius 12735 points

    Hi Hank,

    Can you give me more information on what you mean by unstable? Is the output dropping?

    V5ANA should not be powered before VSYS. You can find this in section 7.4 of the TPS65094x datasheet on page 82.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

                      Fig 1 : VSYS vs V5ANA

                      Fig 2 : RSMRST# waveform

                     and our core-power schematic file.

                      Please give me some suggestion,thanks!

    Hank 

                      

    Edit by Layne J: Post edited to remove the schematic per customer request.

  • 0 in reply to Hank Chang2
    TI__Genius 12735 points

    Hi Hank,

    Can you provide a scope shot confirming THERMTRIPB and SLP_S4B behave as expected after RSMSRTB goes high? The expected sequencing is found in Figure 6-7 on page 41 of the TPS65094x datasheet. 

    Please also provide the values found in the following registers after the device goes through the reset issue:

    1. SHUTDNSRC – offset 0x05
    2. PWR_FAULT_STATUS1 – offset 0xB2
    3. TEMPHOT – offset 0xB5

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

                     I have a question. In my case, the input voltages of buck1, buck4 and buck5 are all connected to the same source. Does this have any impact?

                     In addition, I found in the datasheet that the inputs of buck1, buck2 and buck6 are all greater than 5.6V. If the input of buck1 is only 5V, will it affect it?

                     Thanks!

    Hank

  • 0 in reply to Hank Chang2
    TI__Genius 12735 points

    Hi Hank,

    BUCK1/2/6 can be supplied by 5V with no issues. VSYS supply must be greater than 5.6V to power up the device but supplying the buck controllers with 5V is okay. Supplying BUCK1/4/5 from the same supply is not a problem as long as the supply is capable of supplying the current for all those bucks.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

                     Is the power timing of TPS650942 VSYS> EXT. BUCK5V> PMIC_EN?
                     Are DRV5V_1_6 & DRV5V_2_A connected to LDO5P0?
                     If not, what would be the problem.

    Hank

  • 0 in reply to Hank Chang2
    TI__Genius 12735 points

    Hi Hank,

    The power up timing is VSYS -> LDO5V/3.3V -> Ext. 5V/3.3V VR -> PMICEN according to the power up sequence image found on page 41 of the TPS65094x datasheet.

    DRV5V_1_6 and DRV5V_2_A can be connected to LDO5PO to power the gate drivers. If an external 5V supply is always going to be available when the PMIC is enabled then you can power those pins using the external 5V supply with no issues.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

                      Why does adding a 180uF capacitor to the output of BUCK5 cause BUCK4 and BUCK5 not to work properly?
                      This means that BUCK4 and BUSK5 of TPS650942 are damaged.

    Hank

  • 0 in reply to Hank Chang2
    TI__Genius 12735 points

    Hi Hank, 

    What do you mean by not working properly? How much total capacitance do you have on BUCK5? Can you provide a scope shot of the output of the LX5 pin and the output of BUCK5 when you are seeing this issue?

    Best regards

  • 0 in reply to Hank Chang2
    Prodigy 90 points

    Hi Layne,

                      Please remove the schematic file,

                      Thanks!

    Hank

  • 0 in reply to Hank Chang2
    TI__Genius 12735 points

    Hi Hank,

    I have edited the post and removed the schematic.

    Best regards,

    Layne J