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BQ76920 External Balance FET Selection

Other Parts Discussed in Thread: BQ76920, BQ78350-R1, BQ76920EVM, TIDA-00449

I'm working on designing an open source 12V LiFePo4 BMS, 100A maximum charge and discharge, coupled to an Arduino Zero and 2.8" TFT LCD for control and status of the pack.  I'm designing this system using the BQ76920 / BQ78350-R1 combo.

I'm trying to figure out the application information regarding external balance FETS as referenced in slua749.pdf page 7, where it says:

External cell balancing can be used with the bq769x0 family. An external FET is switched to draw current
from the cell through a resistor. Control for the FET comes from the voltage across one of the Rc input
resistors. When P-channel balance FETs are used the upper resistor is used, see Figure 5. When N-
channel balance FETs are used, the lower resistor is used, see Figure 6. A FET with a defined R DS(ON) at
approximately 1⁄2 the cell voltage is desired. These FETs will typically have a low maximum V GS , so the
gate voltage will usually need to be protected by a zener diode. The gate voltage should be connected
through a resistor to limit the current when the diode conducts. During normal operation the zener will not
conduct. During a heavy load event such as a short circuit, the cell inputs will drop near battery- while the
IC VCn pins will initially be at their normal voltage as shown in Figure 7. The zener diodes will prevent the
high voltage from reaching the gate and most of the input resistor voltage will be dropped across the gate
resistor. The gate resistor current will contribute to the drop of the Cf capacitor voltage, so the gate
resistors should be large. When the short circuit is released, the voltage will reverse on the input filter
resistors and gate protection zeners will conduct in the opposite direction.

1. When it states that the RDS(on) should be half of the cell voltage (charged should be around 3.6v), does this translate into roughly 1.8Ohms or 1.8mOhms?

2. Is it possible to run the external balancing circuit in parallel with an identical circuit that uses an LED with current limiting resistor instead of a power resistor to indicate that the cell is being actively balanced?

3.  What would be a nominal value for the gate protection zener diodes using N-FET?

4.  Would using 2 0.002Ohm 5W sense resistors in parallel utilize the full current sensing range of the AFE without overloading it with up to 100A currents?

  • 1. You will typically want the FET to have a specification at low voltage, perhaps 1.5V or 1.8V.  What Rdson it will have will likely be dependent on the FETs available, and you will need to work with this resistance in your design.  The paragraph is trying to describe that a FET with an Rdson specification at say only 4.5V and 10V may not be suitable for use as a balancing FET.

    2. Yes, this should be possible.  Note that since your balancing resistor should have the cell voltage across it your LED and dropping resistor should be able to be applied across the balance resistor without duplicating other components, depending on the circuit limits.

    3. The gate protection zener should be a few volts below the abs max Vgs of the FET selected.  If you have a 20V abs max Vgs FET then a 15 to 18V zener might be suitable, if abs max Vgs is only 6V then a zener in the 4 V range might be good.

    4. As a concept yes since with RSNS=1 the maximum OCD threshold is 100 mV.  Be sure to consider tolerance of the IC threshold, the resistor tolerances, circuit board and solder resistances and whether the 100A is a must pass or must trip threshold.

  • Thank you for your insight into my questions. 

    I decided to combine elements from the TIDA-00449 reference design and the BQ76920EVM module to come up with my current schematic.  I believe I got all the basic elements correct, the only aspect that I'm currently not sure is since I'm utilizing a 4-cell design, have I correctly shorted VC3 and VC4 together on the BQ76920?

    Thank you for the idea of using the voltage drop on the power resistor for the external cell balancing circuit.

    Once I finish up this page of the schematic, I can start to work on getting at ATSAMDG18 MCU interfaced with the BQ78350-R1.

    7382.circuit.pdf

  • circuit_edit vish_mar22_2016.pdfHello Richard,

    Have made few suggestions on the corrected PDF. attached to the post.  

    (1) bottom of C4 should be GND. should not connect to  V0

    (2) add cap to GND on V0 ( next to R21)

    Shorting VC4 and VC3 implies there are 4 cells per d/s table 8-1 pp 42.

  • Thank you Vish for your corrections. I'm glad you caught the error with the capacitors. As for shorting VC4 and VC3, I assume by your yellow box in my schematic means it is correct, as this will be a 4 cell unit.
  • yes, for a 4 cell unit, shorting VC4/VC3 configuration is correct.
  • Hello Vish.

    A couple of queries with regard to the circuit layout uploaded in the PDF by you.

    1) What is the balancing current for the circuit described in the pdf?

    2) How are the values for Rbal,Rg,Rc to be chosen when external balancing needs to be done.

    Thank you in advance.

  • since this not your IP; I will refrain from answering.

    We also do not encourage forum users to post their company IP(schematics and layout) and only answer

    to their own IP.

    txs

    vish