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bq24251 D+/D- detection algorithm

Keith Keller
Expert 6260 points
Other Parts Discussed in Thread: BQ24251

Hello,

I have some questions regarding the bq24251 D+/D- detection algorithm.

(1) The datasheet states that the D+/D- detection algorithm is only active when the device is in standalone mode (e.g. the host is not communicating with the device and the watch dog timer has expired). With our device in standalone mode, when I connect an SDP to the bq24251 I would expect the device to be put in to Hi-Z mode as defined in figure 19. However, when I do connect an SDP to the bq24251 and read back the registers it is indicating the following register settings:

Reg: 1 Value: 0x40
Reg: 2 Value: 0xEC
Reg: 3 Value: 0x8E
Reg: 4 Value: 0xF8
Reg: 5 Value: 0x02
Reg: 6 Value: 0xA8
Reg: 7 Value: 0xE0

According to these register settings, an SDP was detected but it is not in high impedance mode and the current limit is set to “External ILIM current limit”. But I’m also seeing that the STAT pin is high which indicates to me that it is not charging! This is what would be expected in Hi-Z mode but the register settings seem to indicate that it is not in Hi-Z mode.

My question is: can I trust the register setting readings when the device is in standalone mode?
Or does an I2C read with the device in standalone mode cause the device to switch to host mode which then changes some of the register settings?

It’s not clear from the datasheet if only a I2C write will put the device into host mode or if any I2C activity puts it into host mode.
If that’s the case, how can my host MCU know what’s going on if the act of doing an I2C read causes the register settings to change?

When testing an apple charger:
I can detect all other types of chargers but my Apple charger shows up as an SDP. It’s a relatively new model (Model No. A1265), are there any known issues with detecting certain Apple models? It showing up as an SDP isn’t the end of the world but I’d like to know if there’s an issue

(2) In table 3, why is the default input current limit for an “SDP Good Battery” charge port type Hi-Z instead of 500mA?
It’s my understanding that an SDP can supply up to 500mA so why would the default setting be to disable charging?

(3) Figure 19 references a variable called VBATGD but it is not defined anywhere in the datasheet. What’s the min/typ/max value of VBATGD?

Thank you.

  • 0
    TI__Guru*** 143950 points

    Regarding 1, I need to confirm on the bench.  Each of our parts work slightly differently.  For the 160/260 parts, D+/D- performed at startup in standalone mode sets the current limit for standalone mode only so you can't rely on the current limit registers.  But, you should be able to rely on the D+/D- read only registers.  I will check with the 250 on Tuesday by powering up into a know charging state and see how much current I pull in standalone and then again in host.

    Regarding 2, I understood from the systems engineer (no no longer with the group) that Fig 19 was compliant with an early (draft?) version of BC1.2 spec.

    Regarding 3,  VBATGD or V(BATGOOD) is minimum level that the user defines as a "good", meaning charged enough, battery per BC1.2.  For 250, we set it for 3.4V.