This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ24195: PMID Voltage drop to 4.85V when there is no Vin and Mobile phone connected to PMID pin

Part Number: BQ24195
Other Parts Discussed in Thread: BQ24190,

Hello,

Make Power bank solution by using BQ24195.

PMID Voltage drop to 4.85V when there is no Vin and Mobile phone connected to PMID pin.

Is it normal? 

If not, what can I fix this issue?

Please let me know.

Regards,

Nicky

  • Hey Nicky,

    How much current is your phone attempting to draw from the output of the charger (I_PMID)?

    If it is overloading the charger beyond the 2.1A max it can handle out of PMID, the output voltage may start to droop. Sequentially, most modern mobile phones have a protection on their internal charging IC that can regulate the input voltage (V_PMID of the BQ24190 in this case) by limiting the current draw from the input source to regulate to a certain voltage.

    Lastly, where are you measuring this voltage? Are you measuring directly at the PMID pin of the BQ24190?


    Regards,
    Joel H
  • Hi Joel,

    Charge current(I-PMID) is 0.68A,

    Voltage measured at Capacitor which is connected to PMID pin.

    Tested with BQ24195EVM at the same condition, and PMID voltage is 5V and charge current is 1.27A at that time.

    Attached schematic. Please refer it.

    Regards

    Nicky

    battery_charger.pdf

  • Hey Nicky,

    I am confused here. You have charge current with no input applied at VIN?

    I am also curious what your battery voltage is here (measured at the BAT pin of the charger).


    Regards,
    Joel H
  • Hi Joel,

    Application is Power Bank, and Charge current means that PMID output current at this time.
    The problem is PMID voltage drop when this application works as Power Bank. (No Vin to BQ24195, and PMID pin works as output.)
    At this time, Battery voltage (BAT pin voltage) is around 4.2V.

    Regards,
    Nicky
  • Hey Nicky,

    I went back and looked at your schematic again and noticed that Q6 is facing the opposite direction to what we recommend.

    That body diode is facing the input node with also pulls up on the gate of Q3 to drive the OTG low. 

    Can you remove Q6 and see if OTG functions corrected?

    Regards,

    Joel H

  • Hi Joel,

    Already noticed Q6 direction and changed it, but not applied in schematic yet.
    Is there any other missed part?

    Regards,
    Nicky
  • Hey Nicky,

    Not that I can see, but I would start with that. I would suggest removing Q6 from your current test board and see if this allows OTG to regulate properly.

    Regards,

    Joel H

  • Hi Joel,

    Tested without Q6, but same result.
    Is there any other point to check?

    Regards,
    Nicky
  • Hey Nicky,

    Sorry for my late response. I was on business travel all last week.

    Without Q6, did you verify if the OTG pin is HIGH? Can we also take a look at the register settings?


    Regards,
    Joel H
  • Hi Joel,

    OTG PIN is High.

    And Register setting is as below.

    Register Setting
    00 34
    01 21
    02 C4
    03 01
    04 B2
    05 00
    07 C3

    Regards,
    Nicky
  • Hey Nicky,

    Can you also provide the readout of registers 06, 08, and 09?

    I also went back and looked at your initial post information and saw that this is all when testing with a mobile phone.

    I never asked what the voltage was when there is no load attached to the charger? Additionally, can you also test this will a standard E-load and step up the current slowly, and see if you see the same behavior? You may also use a resistor box. 

    Most mobile phones come equipped with an internal charger that has either some input voltage regulation or input current limiting feature. For us, it's called VINDPM or IINDPM, while other vendors may have different names. 

    Either way, this feature allows the charger in the phone to use as much input power as necessary down (voltage) or up (current) to those specific limits. 

    Regards,

    Joel H

  • Hi Joel,

    Please see below register setting.

    Register setting
    00 34
    01 21
    02 C4
    03 01
    04 B2
    05 00
    06 00
    07 C3
    08 C0
    09 90
    0A 23

    Regards,
    Nicky
  • Hey Nicky,

    Have you consistently seen REG09 report that value when you are in OTG mode?

    Also, have you been able to test the charger in the conditions I mentioned above?


    Regards,
    Joel H
  • Hi Joel,

    REG09 value is consistently 00 during OTG mode.

    Cannot test as you mentioned because don't have E-load.

    Test results are different between EVM and customer board. So, customer wants to know what is the different between EVM and customer board. And why this different symptom is occurred.

    Could you re-check attached schematic and let me know what is the different between EVM circuit and this schematic?

    Regards,
    Nicky
  • Hey Nicky,

    For one of my tests described above, even without an E-load, just check the unloaded output voltage of PMID to see if the charger is regulating correctly in an unloaded condition.

    You also mentioned above that REG09 is consistently 00 during OTG mode, but your response before that shows that REG09 = 90. I am trying to understand the difference between the two register states.

    I also want to double confirm that you physically removed the Q6 FET for this test such that the VBUS pins of the charger are disconnected from the input coming from J1 on your schematic?

    Lastly, I should I have asked earlier for these but can we get a few waveforms of your system in operation? Specifically, I am looking to see V_PMID, V_SW, V_SYS, and if possible I_PMID in several scenarios:
    1) Steady-state Unloaded condition
    2) Transient event of plugging in your load
    3) Steady-state Loaded condition



    Regards.
    Joel H
  • Hi Joel,

    1.  PMID voltage is 5.1V when unloaded. 

    2.  REG 09 value is changed from 09 to 00 when phone charging 

    3.  Tested after Q6 FET removed.

    4. Attached is measured waveform.

    Regards,

    Nicky

    1602.Waveform.zip

  • Hey Nicky,

    One more thing you can try is to load the PMID pin on your board directly with an E-load and monitor the output voltage droop with various load ste;ps.

    I would also re-verify the I_PMID loading current. How did you measure this 0.6A current value?

    I also tested your conditions on our EVM and even loaded it with even more current (~1.1A) and still saw no loss of regulation voltage.


    Regards,

    Joel H
  • Hi Joel,

    Cannot test various load steps because don't have E-Load.
    Current measured by current meter.

    Customer wants to know the difference between EVM and customer circuit.
    And your waveform review result.

    Please check customer circuit again and let me know if there is any check point.

    Regards,
    Nicky
  • Hey Nicky,

    Again, I do not see anything unacceptable on your schematic.

    One thing to check is the saturation current rating your inductor. 

    Additionally, a layout may also be helpful.

    If you do not have an E-load, do you potentially have a power resistor box? 

    Lastly, I would recommend ordering our EVM and testing it in your exact setup to see if this is somehow related to your layout or if this is related to the testing setup.

    Regards,

    Joel H

  • I'm having a very similar problem. Trying to use this chip for a power bank application. The schematics is basically an exact copy of the "typical application".  When boost is enabled by writing 0x6B to reg 1 and periodically resetting the watchdog I get about 5.1 V output voltage when idle. Drops to 4.6 V at 1A load while the battery is at 3.57 V and to 4.15 V with 1.5A load while the battery is at 3.51V . Needless to say the EVM board  works perfectly under the same conditions and is happy to drive 2 A with little voltage drop.

    I thought the inductor could be to blame. Replace with the exact part used on the EVM board, but it didn't change anything. My board is 2 layer, not 4 layer, but there is a solid ground pour under the chip and the important traces are kept very short. I measure the voltage right at the capacitor connected to PMID. What can possibly be wrong?

    Thanks.

      

  • Hi Alex,

    Out of curiosity, are you using the bq24195 or the bq24195L, the L version can only provide an OTG load up to 1A vs. 2A on the regular non-L version.

    I don't see anything obviously wrong on your schematic, besides the missing decoupling caps on BAT pin, not sure if C17 and C18 are them.

    Couple things you could verify:
    -Verify the switch node waveform on your board vs. EVM to make sure the converter is operating as expected (not being forced to max duty cycle or any oscillations, etc.).
    -Try adding more capacitance at PMID.
    - Make sure the power pad of the device is properly connected to GND. Typically 6-9 vias to the ground plane is enough.
  • Thanks for a quick reply.

    Using bq24195 WITHOUT "L".  There is a cap on the BAT pin - a ceramic 10 uF 10 V. Right next to the chip.  C9. The waveform is virtually identical between my board and the eval kit. SW has a frequency of about 1.4 MHz, what looks like 75% duty cycle.   PMID has 3 caps , 22 uF each. One right next to the pi, the other two maybe 1/2 inch away. And I sure have 9 vias to the ground plane. What else could it possibly be?

  • Hello Alex,

    Couple comments on your layout:
    - Do you have a top layer GND copper pour? If not, there's couple caps that have poor ground return layout. I recommend adding a GND copper pour on your top layer and stitch it together with the bottom layer.

    - Many caps, like C9, C4, C101, C17, C2, have a single via or narrow trace as their ground return path. Typically this is fine for low current rails, but on power rails like VBUS,PMID, VBAT this will affect performance of the device.

    Ensure your ground loop on PMID is as optimized as possible. On the current layout, both caps share a single via that goes down to the bottom layer which is segmented by an LED trace. I recommend moving the LED trace to prevent segmenting the ground plane. Also, change your polygon connect style from relief to direct connects.

    The decoupling cap for BAT, C9, has a single very thin trace as the ground loop. Similar to PMID, try to prevent ground segmentation and having a solid ground return path.

    - I see you have pours for SYS and VBUS but they are connected via thin traces to the caps/pins of the device. If possible make these traces thicker and/or incorporate them into a pour.

    You can also use the layout of the EVM as a guideline, the layout is found on the user's guide for the EVM.

  • Thanks for a detailed answer, Fernando. I'll try to mimic the EVM layout much as possible with only 2 layers. Hope having 4 layers is not a necessity as our product is rather cost sensitive.
  • Update: the new PCB still 2 layers, but with improved topology made all the difference and everything works fine.

    One question: I understand that there are built in features in the chip to prevent battery overcharging and over-draining. So is is safe to NOT use a separate protection board that is usually attached to LiIon batteries?

  • Hello Alex,

    Glad to hear the new PCB layout helped.

    Regarding the battery protection, it's recommended to use secondary protection on the battery pack itself to have redundancies in place. In the event of a catastrophic event that may damage the charger, there can still be another level of protection preventing damage to the battery.