(iT MIGHT BE bATTERY mANAGEMENT FORUM QUESTION BUT I ASKED IT HERE AS IT IS RELATED TO FETS)
1. ON PAGE 13 OF SLUU474, THERE IS PARAGRAPH GIVEN
The high input capacitance of the Discharge and Charge MOSFETs can lead to a slow turn off time ifproper drive circuitry is not used. In this EVM, the drive circuit employs a JFET that has a low outputresistance compared to the 1-MΩ resistor across the MOSFET gate when the MOSFET control signal isturned OFF. This low resistance quickly pulls the charge off of the gate of the MOSFET. Fast shutoff timeis desirable in battery management because of the high energy in the cells. Turnoff times of less than onemillisecond can be expected for these 10-mΩ switches (two 0.020 Ω in parallel).
2. NOW ON PAGE 43 OF SLUU474, IN CKT DIAGRAM
JFET ARE - q5 & q6 & THEY ARE PULLING CHARGE FROM q13 & q15 RESPECTIVEY.
3. HOW DOES JFET AFFECTS THE CKT, IT IS ON IN BOTH THE STATES WHETHER Q3 & Q4 ARE ON FOR TURING ON Q13 & Q15.
AS TO TURN OFF JFET, -VE VOLTAGE HAS TO BE APPLIED. BUT HERE VGS>=0.
4. WHEN ONE SAY JFET HAS LOW OUTPUT IMPEDENCE, WHAT DOES THAT MEAN IN THE CKT. WHICH PATH HAS LOW IMPEDENCE- DRAIN TO SOURCE ?
BUT HERE FET HAS ALWAYS ON.
5. WHICH PIN SHOULD BE DRAIN OR SOURCE. I THINK BOTH ARE INTERCHANGEABLE.
6. DO TI HAVE EQUIVALENT PART FOR IT.
The JFETs were added to clamp the gate-to-source on the p-channel FETs in the charge / discharge path to turn them off quickly. When Q3 or Q4 is off, the gate-to-source voltage on the JFET is close to 0V and the JFET will turn on. When Q3 or Q4 is on, the gate of the JFET will be pulled to a lower voltage than the source and the JFET will turn off. The source of the JFET should be connected the resistor divider in the gate drive path. TI does not offer any JFETs in our portfolio.
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