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Understanding "Charge" and "Discharge" function of BQ76930EVM

Other Parts Discussed in Thread: BQ76930EVM, BQ76930, BQ78350, BQ76920, BQ76940

Hello,

I am brand new to the TI battery chipsets, and have been looking at schematic for the BQ76930EVM. I'm having trouble understanding how the charge and discharge FETs are meant to operate. To my way of thinking the charge FET should be activated when you want to apply a charge from an external power source to charge the batteries, and the discharge FET would be activated when you want to control the output of the battery driving a load. When I look at the configuration on the schematic (Page 44 of SLVU925B) it looks as though both the discharge (for Q2) and the charge (for Q4) FETs would need to be activated to have current flow from J1 to J3. I do see the "PFD" node in the middle that creates an alternate path (through Q17) to J3 using the "pre-charge" control, but it still requires Q2 to be activated. I'm not sure how you would integrate a charge system into this configuration? Does this mean that for most operations both charge and discharge need to be active at the same time (or discharge in combination with pre-charge). Any help would be much appreciated. Thanks in advance.

Dan.

  • Hi Dan,

    Each FET blocks current in one direction, so the charge FET controlled by CHG will block charging current, the discharge FET controlled by DSG will block discharge current. These are used in a lithium ion battery system to prevent over charge or over discharge of the cells. The battery should be operated in its safe region by the equipment connected, so normally both FETs will be on, at least when the battery recognized it is in use.  When the external equipment fails to operate the battery in a safe range, the battery will switch the FETs off.  Which FETs switches with which fault depend on the IC design and/or algorithm used for control.  The bq76930 typically switches off only the FET to block the current for the direction of the fault. If the charge FET turns off from overvoltage for example, the discharge FET remains on so the battery can be discharged. Discharge current can flow through the body diode of the charge FET while it is off, but this can lead to heating of the FET and potential damage. Some devices will implement a body diode protection mechanism to turn on the charge FET again if discharge current is flowing even though the cells are still in overvoltage.  Other devices will leave the FET off until the fault recovers and expect the battery designer to size the FET appropriately to handle that reverse current.  The bq76930 gives the determination and decision to the host, the bq78350 or other MCU.  If for example the OV fault is cleared and the FET enabled but the fault re-occurs the host will need to clear the fault and enable the FET again.

    When the charger is a simple CC-CV source and does not know or pay attention to what the battery voltage, the battery may implement a pre-charge circuit to reduce the charge current while battery cell voltages are below a set threshold. The pre-charge current can flow through the discharge FET body diode or through the main FET path if the discharge FET is turned on.

    The circuit function of the bq76930EVM considers the battery as a standalone system such as might exist with a removable battery.  The battery would be connected to a charger or to a load.  If you communicate with the battery in either the charger or load you will need to consider isolation of the signal lines with the low side switching.  If you have the battery implemented in a system with both a simultaneous load and charger you will typically need another level of current control to determine when the battery should be used or charged and when or if the system should operate from the charger. These switching functions are included in some ICs for single or few cell systems, but are not in the bq76930.  The bq78350 does not provide control for directing current between the charger, load and battery, only for protection of the battery.  If using the bq76930 with an MCU, more complex control could be implemented, additional FETs and appropriate FETs would likely be required.

  • Hello WM5295,

    Thank you for the information, it is a big help.

    I do have a follow-up question  based on your response. On page 44 of SLVU925B showing the FETs interconnect for BQ76930EVM it seems that the batteries are intended to go to J1/J2  ("BATT" connection) and the output of the controlled system is intended to go to J3/J4 ("Pack" output) shown below. If I understand correctly the body diode conduction would run from Source to Drain so for Q2 (discharge FET) the FET would be in body diode conduction when discharging so even if the FET was off the battery could still discharge? Same but opposite for Q4 for charge. It seems like they should be the other way around based on your description. Am I missing something?

    Thanks in advance. 

  • Hold on... I just realized this is a low side connection so the current paths are opposite right? Sorry for the trouble!
  • One last question if I may: I have heard from some people that some of the low Rds FETs such as the AOB290L used on Q2 and Q4 in BQ76930EVM are considered well suited for switching applications, but not necessarily constant linear operation. I've been told that for a constant supply that FETs should be run in an SOA and that you often pay the price of having an Rds in the 70m OHM instead of 3.5m OHM as these are rated for. Is there a concern about using low Rds FETs for constant current supply?
    Thanks again.
  • Right, remember it is low side and additionally the schematic is drawn with the positive on the bottom.  For other readers:

    RDS(ON) is typically in the static specifications of the datasheets and we expect the vendor to meet the specification.  In general the linear region of a FET is where the VDS and IDS curves change slope the most, but RDS(ON) is specified at a specific condition.  The AOB290L has worked well on the EVM. It may be best to discuss your concern with a FET expert. 

    Since the EVM's development TI has come out with 60, 80 and 100V N-ch MOSFETs which might be used with the bq76930.  Although none of the devices fit the current footprint, if the board was redesigned today it would use a TI FET.  If you are looking for a MOSFET supplier please consider TI, you might look at the CSD195xx devices.  See www.ti.com/nexfet

  • Great information...I notice that Q4 has Zener diode protection for Vgs with D3, but Q2 does not. Is there a Zener internal to the BQ76930 or is it not needed here?
    Thanks in advance.
  • The CHG and DSG pins of the bq769x0 swing from 0 to 12V nominal.  For the discharge FET this should always be in the range of the FET gate since its source is essentially at 0 V.  The charge FET however can have its source far below ground if the charger is connected, the battery voltage is low and the CHG output is off.   When conditions are met that the charge FET turns on, the external p-ch FET will send current into the gate circuit to pull it to 12V, this may be too high instantaneously for the MOSFET.  

    Consider a 10 cell 42V pack discharged to 30V.  If it is hot enough that charging is inhibited and plugged into a 42V charger, the PACK- and the charge FET source is at -12V with respect the the bq76930 VSS and battery-.  When the battery cools such that CHG turns on, CHG would go to 12V, the FET gate will go from -12V to 12V or from 0 to 24V with respect to its source.   FET experts are reluctant to say if the FET will turn on fast enough to pull up PACK- to prevent damage to the FET.  The zener diode will limit  the Vgs to a safe level and drop additional voltage across the series resistance to CHG or pull down the CHG pin.   For low voltage packs such as with the bq76920 the voltage differences may not be large enough to need the zener.  For the bq76930 and bq76940 the need is greater.

    There is a clamp internal to the bq76930 on the CHG pin, but this is to VSS and is to limit the pin voltage when PACK- is pulled to PACK+ during a discharge protection fault with load on the PACK.  Note the 500 uA test current for the clamp is high and its maximum voltage is above the VGS abs max of typical FETs which would be used on the CHG pin.  Since there is no spec at lower current, if this is a concern you may want a zener on CHG to VSS as well.  A 15 to 18V zener might be used,  similar to the diode at Q4 you want to avoid leakage into the diode when CHG is high.

  • Thanks for your help.
    Dan.